Abstract: A portable computer can be “hot” docked to one or more expansion devices, such as a drive wedge and a port replicator. As such, the expansion devices can be connected to and disconnected from the portable computer while portable computer is powered on and fully operational. The portable computer includes control logic that detects when an expansion device is connected to or disconnected from the portable computer and asserts an SMI or equivalent interrupt signal to the computer's CPU to initiate a sequence of events by which the computer determines whether an expansion device has been connected or disconnected. If the CPU determines that the expansion device has been connected to the computer, the CPU appropriately reconfigures itself to communicate with the expansion device. If the expansion device is disconnected, the CPU also appropriately reconfigures itself to preclude communications with the disconnected device.

Abstract: Private devices are implemented on the secondary interface of PCI bridge by re-routing the activation of device select signals (IDSEL) during the address phase of a Type 0 configuration operation on the secondary bus in response to a Type 1 configuration operation on its primary bus. Under control of a mask register and device select reroute circuit, if a configuration command on the primary interface attempts to activate the IDSEL line associated with one of the private, or reroute, devices on the secondary interface, a different IDSEL is activated to select a monitoring device on the secondary interface.

Abstract: A method of optimizing the topology of the IEEE 1394 serial bus having a plurality of nodes each with communication ports, comprises the steps of prioritizing the nodes according to the number of the ports and the transmission speed, connecting a non-used port of the node of the first priority with a port of the node of the second priority, and repeating the previous step until all of the nodes are connected together, whereby the nodes are connected through the ports according to priority order.

Abstract: A case for an electronic device, which includes a first protective material that maintains the electronic device within the case, and at least one controlling interface that is in electrical communication with said electronic device, and disposed on the first protective material. Through the controlling interface, the user can operate an electronic feature of the electronic device. Electrical communication between the controlling interface and the electronic device can be carried out, at least in part using wireless communication means. Further, a connection port can included for transferring electrical signals between the electronic device and the controlling interface. The connection port can be attached to the first protective material to avoid separation of the port from the case.

Abstract: An opaque memory region for a bridge of an I/O adapter. The opaque memory region is inaccessible to memory transactions which traverse the bridge either from a primary bus to secondary bus or secondary bus to primary bus. As a result, memory transactions which target the opaque memory region are ignored by the bridge, allowing for the same address to exist on both sides of the bridge with different data stored in each. The implementation of the opaque memory region provides a means to complete memory transactions within I/O adapter subsystem memory, hence, relieving host computer system memory resources. In addition, a number of I/O adapters can be used in a host computer system where the host and all the I/O devices use some of the same memory addresses.

Abstract: A bus interface circuit arrangement and method. In various embodiments, a bus interface circuit arrangement interfaces with a bus functioning in accordance with a bus protocol. The bus interface circuit arrangement includes a bus interface circuit having a port arranged to be coupled to the bus. The bus interface circuit provides physical and link layers of the bus protocol. A bus processing block, implemented with a programmable device, is coupled to the bus interface circuit and is configured to perform selected processing in response to selected bus messages. A filter circuit, also implemented with a programmable device, is coupled to the bus interface circuit and to the bus processing block. The filter circuit is configured to direct bus messages to a selected one of the bus interface circuit and the bus processing block responsive to a code in the bus message.

Abstract: A crossbar switch is disclosed. The crossbar switch comprises a plurality of input sorting units and a plurality of merge and interleave units. Each input sorting unit is capable of receiving from a respective device an access request to any one of a plurality of physical memory devices. Each merge and interleave unit is capable of arbitrating among competing access requests received from any of the input sorting units, selecting one of the competing access requests and forwarding the selected request for implementation on a respective memory device. Also disclosed is method implemented by the crossbar switch.

Abstract: An anti-starvation interrupt protocol for use in avoiding livelock in a multiprocessor computer system is provided. At least one processor is configured to include first and second control status registers (CSRs). The first CSR buffers information, such as interrupts, received by the processor, while the second CSR keeps track of the priority level of the interrupts. When an interrupt controller receives an interrupt, it issues a write transaction to the first CSR at the processor. If the first CSR has room to accept the write transaction, the processor returns an acknowledgement, whereas if the first CSR is already full, the processor returns a no acknowledgment. In response to a no acknowledgment, the interrupt controller increments an interrupt starvation counter, and checks to see whether the counter exceeds a threshold. If not, the interrupt controller waits a preset time and reposts the write transaction.

Abstract: A method for processing a PCI-X transaction in a bridge is disclosed, wherein data is retrieved from a memory device and is stored in a bridge then delivered to a requesting device. The method may comprise the acts of allocating a buffer in the bridge for the PCI-X transaction, retrieving data from a memory device, wherein the data comprises a plurality of cachelines, storing the plurality of cachelines in the buffer, wherein the plurality of cachelines are tracked and marked for delivery as the plurality of cachelines are received in the buffer, and delivering the plurality of cachelines to the requesting device in address order, the plurality of cachelines transmitted to the requesting device when one of the plurality of cachelines in the buffer aligns to an ending address of an allowable disconnect boundary (ADB) and the remaining cachelines are in address order.

Abstract: A system and technique provides fast acknowledgement and servicing of interrupt sources coupled to a high latency path of an intermediate node of a computer network. An external device coupled to the high latency path is provided with a separate interrupt signal for each type of interrupt supported by a processor of the intermediate node. Each interrupt signal is directly fed to an interrupt multiplexing device over a first low latency path. The multiplexing device is accessible to the processor through a second low latency path. The external device asserts an interrupt by “pulsing” an appropriate interrupt signal to the multiplexing device. The multiplexing device maintains a current counter for each interrupt signal and increments that counter every time an interrupt pulse is detected. In addition to the counter, the multiplexing device maintains a status bit for each interrupt.

Abstract: Systems, devices, structures, and methods are provided to allow resources to be shared among a plurality of processors. An exemplary system includes a mechanism to grant exclusive control of a resource to a processor, while at the same time, the fast memory of such a processor is maintained in a coherent state. An exemplary structure includes data structures that help to identify the portion of the fast memory of the processor to be maintained in a coherent state. An exemplary method includes a determination of past and present processors that have had access to the resource so as to maintain the coherency of the fast memory of the processor.

Abstract: A latency-independent interface between hardware components, such as a hard disk controller (HDC) and a read/write (R/W) channel or a read channel (RDC) supports high read and write latencies of greater than one sector. Such an interface also supports a split sector format and multiple mark format. In addition to read and write clock signals, the interface comprises a data gate signal that controls the transfer of data between the the HDC and R/W channel, and a media gate signal that controls transfer of mode selection information from the HDC to the R/W channel and also controls the transfer of data between the R/W channel and a disk. The media. gate signal replaces the conventional read and write gate control signals. A buffer attention signal is also provided.

Abstract: Apparatus and methods are provided for efficiently implementing logical-device reservations in a cluster computer system. The apparatus includes cooperating controllers programmed in firmware around a distributed reservation table. The apparatus manages access to a logical device, with first and second nodes with respective bus controllers communicatively coupled to each other and to a logical device by means of a bus. The first controller receives a request to reserve the logical device and, in response, communicates a reservation request for the logical device over the bus to the second controller for execution by the second controller. In response to the communicated reservation request, the second controller reserves the logical device for the first node.

Abstract: A matrix of routing cells forming a cross-bar decoder (70). Signal triplets (84, 86, 88) coupled to the cross-bar decoder (70) are assigned a priority. A register (50) provide outputs to the cross-bar decoder (70) to either activate or deactivate routing of the triplet signals (84, 86,88) through the cross-bar decoder (70). The routing cells (72-82) are arranged in a matrix of columns and rows, where the triplet signals are applied to the row routing cells (72, 74, 76) and are extracted at the column routing cells (76, 80, 82). When a routing cell in a row is enabled to couple signals to an output, it disables all other lower priority routing cells in its column so that they cannot route signals to that output. Based on the automatic disabling of routing cells by others, the signals ripple through the cross-bar decoder (70) until all high priority I/O pins are used.

Abstract: An information processing device, method thereof and a recording medium for easily switching input signals. A broadcast connection and a point-to-point connection are established between the receive device and the transmit device. When the user commands the canceling of the P.P. connection established for the receive device or the transmit device, only the broadcast connection remains established. In this state, the user receives signals on a receive device sent from the desired transmit device, and commands the restoring of the P.P. connection with the desired transmit device. The switching of input signals to the receive device is in this way performed by temporarily canceling the P.P. connection.

Abstract: A parallel SCSI host adapter includes a SCSI bus port and a host I/O bus port. The parallel SCSI host adapter takes a snapshot of state data for a first data channel coupling the SCSI bus port to the host I/O bus port following receipt of a complete Packetized SCSI protocol information unit having a context from the SCSI bus port. Following the snapshot, another Packetized SCSI protocol information unit for the same context is transferred over the first data channel. Since the snapshot requires substantially no time delay relative to a time delay associated with saving the state data in a hardware I/O command block for the context, latency between the information units for the same context is minimized in the parallel SCSI host adapter.

Abstract: A method of and apparatus for communicating data using a hub. The method includes the step of buffering a single transfer request received at a hub during a transaction between the hub and a host controller, where the single transfer request is to be performed between the hub and an agent to generate a result. The method then includes the step of determining whether a transfer inquiry received at the hub from the host controller corresponds to the result.

Abstract: A method and apparatus are provided for operating a hot plug system. A first device may determine whether the system is to operate in one of a parallel mode or a serial mode. A second device may control a mode of the chipset based on the determination of the first device. The second device may include logic, a first multiplexer, a second multiplexer, a first converter and a second converter all provided on the chipset.

Abstract: A circuit for use with a PC16550D UART in 16450 polling mode that will filter DR bit oscillations. The circuit latches the value of the Line Status Register during the valid data portion of a LSR register read cycle, deasserts the read strobe, delays to allow the data bus values to float, applies the latched values of the LSR to the data bus, then asserts a ready signal to the microprocessor. If the UART access is not a read cycle to the LSR, the delay time is bypassed and the UART access cycle proceeds normally.

Abstract: A method for allocating a channel in a digital device having a digital interface such as the IEEE1394. The method for allocating a channel to a specific output plug of a digital device having a digital interface, in which a predetermined relationship with a predetermined part of another digital device is set in accordance with a specification related to a digital interface, includes the steps of calculating a channel number to be allocated to the output plug in accordance with a condition of the digital interface specification, and determining whether the calculated channel number can be allocated to the output plug. If it is determined that the calculated channel number can be allocated, then the calculated channel number is allocated to the output plug.