Abstract: Improved circuitry for connecting the memory array to a data bus allows for high speed accessing of the memory array. Sense amplifier latches are coupled to each column of memory cells. The latched sense amplifiers are coupled to decoders which, in turn, are coupled to data amplifiers. The data amplifiers are coupled to a data bus. Data being read from or written to the memory cells is via the sense amplifier latches, the decoders, and data amplifiers.

Abstract: An adapter for a memory device for connecting a detachable memory device to an AT attachment (ATA) interface of a host computer and a connecting method using the adapter are presented. With a conventional adapter which is not supplied with a number of heads and a number of sectors per track of the memory device in advance, the actual numbers of the memory area of the memory device may be different from those supplied the adapter for a memory device. This prevents the memory device from being normally accessed in a cylinder head sector (CHS) mode by the adapter. The adapter for a memory device according to the present invention identifies a file format of data stored in the memory area in the memory device, and retrieves and saves data about the number of heads and the number of sectors per track. Even if the adapter is not previously supplied with the number of heads and the number of sectors per track of the memory device, it accordingly allows the memory device to be accessed in the CHS mode.

Abstract: A method and system for a multi-phase net refresh on a bus bridge interconnect, the interconnect comprising a number of nodes, a bus bridge, and a number of buses, are described. In one embodiment, a primary bus is acquired by communicating with other bus bridges on the buses. A secondary bus is breached to acquire the secondary bus. In addition, the primary bus and the secondary bus are committed.

Abstract: A cable, adapter, or converter device is disclosed that enables a peripheral device (e.g., external display) normally connected only through a non-USB port to communicate with a host computer via a USB port in addition to its non-USB port. DDC-formatted signals from the peripheral device are converted to the appropriate format for input through the USB port, and signals transmitted to the peripheral device from the USB port are converted to the format recognizable by the external peripheral, allowing access to peripheral features via the host system.

Abstract: A matrix of routing cells forming a cross-bar decoder (310). Signal triplets are coupled through the cross-bar decoder (310) based on control by a microprocessor. A register (50) provide control signals to the cross-bar decoder (310) to either activate or deactivate routing of the triplet signals through cells of the cross-bar decoder (310). The routing cells are arranged in a matrix of columns and rows. Each row of cells is associated with a common data signal input, and each column of the matrix is associated with a common I/O pin. The cells are individually enabled by the microprocessor so that any data signal can be coupled to any of the I/O pins. In addition to routing data signals through the cells, other signals are also routed through the cells.

Abstract: A communication interface circuit transfers signals between a TTL microcontroller and a RS232 device while avoiding level translation. The interface circuit includes two switch elements. A first switch element is connected between the TTL receive terminal and the ground supply. The second switch element includes a first node that is an electrical communication with the TTL transmit data terminal, the RS232 transmit data terminal and the RS232 receive data terminal, a second node in electrical communication with the first TTL power supply and a control node in electrical communication with the TTL receive data terminal. The interface circuit is configurable to a first switching state in which electrically connects the first TTL power supply terminal to the RS 232 receive data terminal.

Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

Abstract: In order to allow a computer system in a multiple system architectures to continue operating while another system has control over common devices, a set of registers is provided for that computer system and the other computer systems in the computer architecture. A switch isolates the set of registers from other computer systems that do not need to access the particular register set. The switch also provides isolation of the computer system from the commonly controlled input and output peripheral devices. The computing systems may utilize similar processors or CPUs or they may be dissimilar processors or CPUs.

Abstract: An apparatus and method for distributing data transmission from a plurality of data input queues in a memory buffer to an output. The method includes associating a priority indicator with each data input queue, determining a priority indicator having a highest priority level among the plurality of priority indicators and selecting the data input queue associated with the priority indicator having the highest priority level to transmit to the output.

Abstract: A source cache transfers data to an intermediate cache along a data connection. The intermediate cache is provided between the source cache and a target, and includes a memory array. The source cache may also transfer data to the target along the data connection while bypassing the memory array of the intermediate cache.

Abstract: Customer requirements for portable computers are grouped into logical functional groupings, which are further grouped into logical bandwidth levels. On the notebook side, all required signals for a specific logical functional grouping are combined into a single carrier with the necessary bandwidth for the signals within the logical bandwidth level. This combined signal is then passed through a docking connector. The individual signals are regenerated on the docking solution side of the connector. Logic on both the notebook and docking solution sides of the connector enables the respective devices to identify which carrier bandwidths are supported on both sides of the docking connector and settle on the greatest common denominator. Additionally, the signals combined into the carrier can be programmed, in which case the docking solution and the notebook negotiate the features that are and are not supported in each individual case.

Abstract: A method for controlling a bus in a digital interface is disclosed. In the present method, after a self identifying process when a bus reset occurs, a determination is made whether a node which needs to transmit isochronous data is a new node which needs to newly transmit isochronous data or a previously connected node which had been transmitting isochronous data before the bus reset. Thereafter, priority is given to previously connected nodes in allocating channels and bandwidth to previously connected node(s).

Abstract: Contention-based method and system are provided for generating reduced number of interrupts upon completing one or more commands. Each interrupt indicates the availability of data for transfer from a host adapter to a processor. The host adapter is coupled to one or more I/O devices over a bus. One or more I/O commands are received for transferring data between the processor and one or more I/O devices. Then, the contention for the bus among the I/O devices is monitored to determine how many devices are arbitrating for the bus.

Abstract: A communication system has multiple communication buses and multiple bus controller cards each supplying at least two independent channels of communication between one or more hosts and the communication buses. One of the controller cards is designated as a primary controller card for managing the communication buses and resetting the communication buses such that if a controller card is inserted to or removed from the system then the buses are reset.

Abstract: A dual mode memory interface includes a bus switch and a register/buffer operatively coupled to the bus switch. The dual mode memory interface may include, operatively coupled to the bus switch and the register/buffer, enable/disable pins configured so that only one of the bus switch and the register/buffer is active at a time. The bus switch may be a transistor configured as a pass gate. The dual mode memory interface may be implemented in a single integrated circuit package. The dual mode memory interface may further include a system controller for detecting a type of memory module connected to the dual mode memory interface and enabling one of the bus switch and register/buffer based on the type of memory module detected.

Abstract: A method and system of managing resources in a host bridge by determining whether resources are deficient, preventing a second device from obtaining further resources and if this measure does not enable a first device to obtain resources, guaranteeing all resources to the first device.

Abstract: A peripheral device and a method for operating the peripheral device for automatic installation, in which the method includes coupling the peripheral device to a computer and sending a first device identification from the peripheral device to the computer. The peripheral device emulates a device of a type determined by the first device identification, including transferring a driver from the peripheral device to the computer. Then, the peripheral device sends a second device identification from the peripheral device to the computer, such that the sent device identification is for a device supported by the driver transferred to the computer. The peripheral device is then operates by interacting with the driver on the computer.

Abstract: The switch input processing module has: a control unit; a first external connection terminal to which either an analog signal of an analog signal system or a serial signal of a serial signal system is supplied; an analog signal transmission and serial signal transmission line which is disposed between the first external connection terminal and the control unit; and a second external connection terminal to which a determination signal indicating that either the analog signal system or the serial signal system is connected to the first external connection terminal is supplied. When the control unit determines that the determination signal indicates connection of the serial signal system, the control unit makes the serial signal transmission line conductive. When the control unit determines that the determination signal indicates connection of the analog signal system, the control unit makes the serial signal transmission line nonconductive.

Abstract: A round robin bus arbitrator that prevents bus starvation caused by an inbound buffer becoming full and forcing repetitive retries by an agent. The arbitrator performs a rotating scan of the request lines of multiple potential bus requesters. When a request is detected, the arbitrator stops, grants the request, and resumes scanning after the requester takes control of the bus. If the data buffer on a write operation becomes full and cannot accept any more data, a signal so indicating is sent to the arbitrator. The arbitrator then stops scanning, or refuses to resume scanning if it is already stopped, until the buffer indicates it is no longer full. The next requester that is granted the bus is therefore not confronted with a full buffer, and not thereby forced to abort the request and make a retry. The invention avoids bus starvation caused by a second bus requestor repeatedly being given a retry response because the buffer is repeatedly filled up by an earlier bus requestor.

Abstract: A network switch is disclosed for resolving requests from a plurality of host initiators by scheduling access to a plurality of storage systems. The network switch comprises a plurality of multi-port switches interconnected to form a switched fabric, the multi-port switches for routing requests to the plurality of storage systems and for receiving scheduling data from each of the plurality of storage systems. The network switch further comprises a memory for storing the scheduling data, and a microprocessor, responsive to the scheduling data stored in the memory, for executing a scheduling algorithm to schedule the requests. The scheduling data is transferred automatically from each storage system to the memory through the multi-port switches without the microprocessor requesting the scheduling data from each storage system.