Abstract: A structure may include an interconnect-level dielectric layer containing a dielectric material and overlying a substrate, and a metal interconnect structure embedded in the interconnect-level dielectric layer and including a graded metallic alloy layer and a metallic fill material portion. The graded metallic alloy layer includes a graded metallic alloy of a first metallic material and a second metallic material. The atomic concentration of the second metallic material increases with a distance from an interface between the graded metallic alloy and the interconnect-level dielectric layer. The graded metallic alloy layer may be formed by simultaneous or cyclical deposition of the first metallic material and the second metallic material. The first metallic material may provide barrier property, and the second metallic material may provide adhesion property.

Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.

Abstract: A three-dimensional flash memory device including a lower and upper word line stack; a cell channel structure; and a dummy channel structure, wherein the cell channel structure includes a lower cell channel structure; an upper cell channel structure; and a cell channel enlarged portion between the lower and upper cell channel structures and having a width greater than that of the lower cell channel structure, wherein the dummy channel structure includes a lower dummy channel structure; an upper dummy channel structure; and a dummy channel enlarged portion between the lower and upper dummy channel structures, the dummy channel enlarged portion having a width greater than that of the lower dummy channel structure, wherein a difference between the width of the dummy channel enlarged portion and the lower dummy channel structure is greater than a difference between the width of the cell channel enlarged portion and the lower cell channel structure.

Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.

Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.

Abstract: A semiconductor device including a semiconductor chip having a first surface and a second surface opposite to the first surface, a first heat dissipation member on the second surface of the semiconductor chip, the first heat dissipation member having a vertical thermal conductivity in a direction perpendicular to the second surface, and a horizontal thermal conductivity in a direction parallel to the second surface, the first vertical thermal conductivity being smaller than the first horizontal thermal conductivity, and a second heat dissipation member comprising a vertical pattern penetrating the first heat dissipation member, the second heat dissipation member having a vertical thermal conductivity that is greater than the vertical thermal conductivity of the first heat dissipation member may be provided.

Abstract: A method comprises forming a gate structure over a semiconductor substrate; forming an etch stop layer over the gate structure and an ILD layer over the etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer into the etch stop layer, resulting in a sidewall of the etch stop layer being exposed in the gate contact opening; oxidizing the exposed sidewall of the etch stop layer; after oxidizing the exposed sidewall of the etch stop layer, performing a second etching process to deepen the gate contact opening; and forming a gate contact in the deepened gate contact opening.

Abstract: A semiconductor device includes an interconnect including (i) a first layer, and (ii) a second layer provided on the first layer and including copper. The device also includes a plug provided on the interconnect and including (a) a third layer including titanium and nitrogen, and (b) a fourth layer provided on the third layer and including tungsten. A concentration of chlorine in the third layer is less than or equal to 5.0×1021 atoms/cm3, and a concentration of oxygen at the interface between the third layer and the fourth layer is less than or equal to 5.0×1021 atoms/cm3.

Abstract: The present disclosure provides a fabrication method that includes providing a workpiece having a semiconductor substrate that includes a first circuit area and a second circuit area; forming a first active region in the first circuit area and a second active region on the second circuit area; forming first stacks with a first gate spacing on the first active region and second gate stacks with a second gate spacing on the second active region, the second gate spacing being different from the first gate spacing; performing an ion implantation to introduce a doping species to the first active region; performing an etching process, thereby recessing both first source/drain regions of the first active region with a first etch rate and second source/drain regions of the second active region; and epitaxially growing first source/drain features within the first source/drain regions and second source/drain features within the second source/drain regions.

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a first die on a board, attaching an interposer on a top surface of the first die, and attaching a second die on the top surface of the first die that is adjacent the interposer, wherein the second die is offset from a center region of the first die. A first wire conductive structure may be attached to the second die that extends from the second die to a top surface of the interposer. A second wire conductive structure is attached to the interposer and extends from the interposer to the board.

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical.

Abstract: A semiconductor device includes a first universal device formed over a substrate, an isolation structure over the first universal device, and a second universal device over the isolation structure. The first universal device includes a first source/drain (S/D) region formed over the substrate, a first channel region over the first S/D region, a second S/D region over the first channel region. The second universal device includes a third S/D region positioned over the isolation structure, a second channel region over the third S/D region, a fourth S/D region over the second channel region. The first universal device is one of a first n-type transistor according to first applied bias voltages, and a first p-type transistor according to second applied bias voltages. The second universal device is one of a second n-type transistor according to third applied bias voltages, and a second p-type transistor according to fourth applied bias voltages.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first through substrate via (TSV) within a substrate. The first TSV comprises a first doped region extending from a top surface of the substrate to a bottom surface of the substrate. A conductive via overlies the top surface of the substrate and is electrically coupled to the first TSV.

Abstract: A display device may include a hole, a display element, a switching element, a groove, a planarization layer, and a cover layer. The switching element may be electrically connected to the display element. The encapsulation layer may cover the display element. The groove may be located between the hole and the display element. A portion of the planarization layer may be located between a first edge of the planarization layer and a second edge of the planarization and may be located in the groove. The first edge of the planarization layer may be located closer to the display element than the second edge of the planarization layer. The cover layer may at least partially cover the first edge of the planarization layer.

Abstract: The present invention relates to an integrated electronic circuit and method of making comprising a first transistor (1) and a ferroelectric capacitor (2). The ferroelectric capacitor (2) comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor (1).

Abstract: Disclosed are a semiconductor structure and a forming method thereof.

Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes: a substrate made by a first material or a first material-composite; an absorption layer made by a second material or a second material-composite, the absorption layer being supported by the substrate and the absorption layer including: a first surface; a second surface arranged between the first surface and the substrate; and a channel region having a dopant profile with a peak dopant concentration equal to or more than 1×1015 cm?3, wherein a distance between the first surface and a location of the channel region having the peak dopant concentration is less than a distance between the second surface and the location of the channel region having the peak dopant concentration, and wherein the distance between the first surface and the location of the channel region having the peak dopant concentration is not less than 30 nm.

Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

Abstract: A light emitting device is disclosed. In an embodiment a light-emitting device includes a pixel comprising at least three sub-pixels, wherein the at least three sub-pixel include a first sub-pixel including a first conversion element, wherein the first conversion element includes a green phosphor, a second sub-pixel including a second conversion element, wherein the second conversion element includes a red phosphor and a third sub-pixel free of a conversion element, wherein the third sub-pixel is configured to emit blue primary radiation, wherein each sub-pixels has an edge length of at most 100 ?m, and wherein the pixel is a linear chain of sub-pixels and a plurality of pixels is arranged in a two dimensional ordered pattern so that a first sub-pixel is never adjacent to a third sub-pixel in a vertical direction and in a horizontal direction of the ordered pattern.