Patents Examined by Kathleen Duda
  • Patent number: 9429840
    Abstract: A pattern forming method includes: (i) a step of forming a first film by using an actinic ray-sensitive or radiation-sensitive resin composition (I), (ii) a step of exposing the first film, (iii) a step of developing the exposed first film by using an organic solvent-containing developer to form a negative pattern, (iv) a step of forming a second film on the negative pattern by using a specific composition (II), (v) a step of increasing polarity of the specific compound present in the second film, and (vi) a step of removing a specific area of the second film by using the organic solvent-containing remover.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: August 30, 2016
    Assignee: FUJIFILM Corporation
    Inventors: Kei Yamamoto, Ryosuke Ueba
  • Patent number: 9425072
    Abstract: A method for fabricating a semiconductor device includes forming an etching target layer over a substrate including a first region and a second region; forming a hard mask layer over the etching target layer; forming a first etch mask over the hard mask layer, wherein the first etch mask includes a plurality of line patterns and a sacrificial spacer layer formed over the line patterns; forming a second etch mask over the first etch mask, wherein the second etch mask includes a mesh type pattern and a blocking pattern covering the second region; removing the sacrificial spacer layer; forming hard mask layer patterns having a plurality of holes by etching the hard mask layer using the second etch mask and the first etch mask; and forming a plurality of hole patterns in the first region by etching the etching target layer using the hard mask layer patterns.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: August 23, 2016
    Assignee: SK Hynix Inc.
    Inventors: Jun-Hyeub Sun, Sung-Kwon Lee, Sang-Oh Lee
  • Patent number: 9412612
    Abstract: A method of forming a semiconductor device is disclosed. A substrate having a first area and a second area is provided. A target layer and a hard mask layer are sequentially formed on the substrate in the first area and in the second area. Transfer patterns are formed in a spacer form on the hard mask layer in the first area. A photoresist layer is formed directly on the hard mask layer, and covers the transfer patterns and the hard mask layer in the first area and in the second area. The photoresist layer in the first area is removed. The hard mask layer is patterned by using the transfer patterns as a mask.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 9, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Chin-Cheng Yang
  • Patent number: 9411237
    Abstract: In some embodiments, a method of forming an etch mask on a substrate is provided that includes (1) forming a resist layer on a substrate; (2) exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions; (3) performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber; and (4) dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer. Other embodiments are provided.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: August 9, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Peng Xie, Christopher Dennis Bencher, Huixiong Dai, Timothy Michaelson, Subhash Deshmukh
  • Patent number: 9405199
    Abstract: A method of forming a resist pattern, and a film including a metal-containing compound formed on the resist pattern while developing the resist pattern. The method uses an organic solvent developer liquid, in which a metal compound capable of generating a hydroxyl group upon hydrolysis is dissolved in an organic solvent that does not have a functional group that reacts with the metal compound.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: August 2, 2016
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Mai Sugawara, Kiyoshi Ishikawa
  • Patent number: 9395629
    Abstract: Present example embodiments relate generally to semiconductor devices, masks, wafers, and methods of fabricating semiconductor devices, masks, and wafers. Example methods comprise providing a substrate having a photoresist layer. Example methods further comprise providing a mask having a substantially rectangular pattern and an elongated pattern, at least a portion of the elongated pattern positioned at least proximate to a corner of the substantially rectangular pattern, wherein the elongated pattern extends outwardly from the substantially rectangular pattern. Example methods further comprise forming a substantially rectangular shaped pattern on the photoresist layer resembling the substantially rectangular pattern using a cooperation of the substantially rectangular pattern and the elongated pattern.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: July 19, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Feng-Nien Tsai
  • Patent number: 9389511
    Abstract: A method for forming patterns of organic polymer materials. The method can be used to form a layer with two patterned organic polymer materials. The photoresist and solvents used in the photoresist deposition and removal steps do not substantially affect the organic polymer materials.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: July 12, 2016
    Assignee: Cornell University
    Inventors: Evan L. Schwartz, Wei Min Chan, Jin-Kyun Lee, Sandip Tiwari, Christopher K. Ober
  • Patent number: 9377687
    Abstract: A method of manufacturing a pattern includes forming a pattern material layer on a substrate, forming a protective layer on the pattern material layer, forming a resist layer on the protective layer, selectively exposing the resist layer to light, and developing the selectively exposed resist layer.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: June 28, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jun Chun, Ji-Hyun Kim, Sung-Kyun Park, Jeong-Min Park, Jung-Soo Lee, Jin-Ho Ju
  • Patent number: 9366966
    Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate, the method includes applying a photoresist layer comprising a photoacid generator to a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: June 14, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Peng Xie, Ludovic Godet
  • Patent number: 9337032
    Abstract: A method of forming a pattern of a semiconductor device includes providing a substrate, forming a photoresist layer by coating a resist composition including an acid generator and a first resin, the first resin having an acid-labile group, exposing the photoresist layer, forming a photoresist pattern by negatively developing the photoresist layer using a developing solution including an organic solvent, coating a capping composition including a second resin and the organic solvent on the substrate having the photoresist pattern formed thereon, and attaching a capping layer on upper and side surfaces of the photoresist pattern, by baking the capping composition and developing the capping composition using the developing solution including the organic solvent.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: May 10, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-Rae Lee, Yool Kang, Seong-Ji Kwon
  • Patent number: 9324563
    Abstract: Methods of forming patterns are provided. The methods may include sequentially forming an etch-target layer and a photoresist layer on a substrate, exposing two first portions of the photoresist layer to light to transform the two first portions into two first photoresist patterns and exposing a second portion of the photoresist layer to light to transform the second portion into a second photoresist pattern disposed between the two first photoresist patterns. The method may also removing portions of the photoresist layer to leave the two first photoresist patterns and the second photo resist pattern on the etch-target layer such that the etch-target layer is exposed.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: April 26, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoungmi Kim, Joo-Hyung Yang, Jaeho Kim, Jungsik Choi
  • Patent number: 9323155
    Abstract: A method of lithography patterning includes forming a first resist pattern on a substrate, wherein the first resist pattern including a plurality of openings. A second resist pattern is formed on the substrate and within the plurality of openings of the first resist pattern, wherein the second resist pattern includes at least one opening therein on the substrate. The first resist pattern is removed to uncover the substrate underlying the first resist pattern.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: April 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Kuang Chen, Hsiao-Wei Yeh, Chih-An Lin, Chien-Wei Wang, Feng-Cheng Hsu
  • Patent number: 9274432
    Abstract: A method for isolating microstructural regions or features on a surface for electrochemical experimentation comprising polishing a metal sample, coating the metal sample with a photoresist, selecting a region of interest of the metal sample, exposing the region of interest with light energy, developing the exposed photoresist and creating a developed region.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 1, 2016
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Farrel Martin, Alberto Píqué, Raymond C Y Auyeung, Steve Policastro
  • Patent number: 9268223
    Abstract: A conductive metal pattern is formed in a polymeric layer that has a reactive polymer that comprises (1) pendant groups that are capable of providing pendant sulfonic acid groups upon exposure to radiation, and (2) pendant groups that are capable of reacting in the presence of the sulfonic acid groups to provide crosslinking. The polymeric layer is patternwise exposed to provide a polymeric layer comprising non-exposed regions and exposed regions comprising a polymer comprising pendant sulfonic acid groups. The exposed regions are contacted with electroless seed metal ions to form a pattern of electroless seed metal ions. The electroless seed metal ions are reduced to provide a pattern of electroless seed metal nuclei that are then electrolessly plated with a conductive metal.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: February 23, 2016
    Assignee: EASTMAN KODAK COMPANY
    Inventors: Mark Edward Irving, Allan Wexler, Grace Ann Bennett, Kimberly S. Lindner
  • Patent number: 9268228
    Abstract: Various techniques for patterning a substrate are disclosed. Specifically, implantation of the first species into an anti-reflective coating layer is contemplated to reduce stress in the layer that may be generated during the exposure stage or development stage. During these steps, the resist layer or the resist structure may under mechanical changes (e.g. shrinkage) while it is in contact with the anti-reflective layer. Such changes may introduce stress in the anti-reflective layer, which may contribute to excessive line edge roughness (LER) or line width roughness (LWR). By implanting the first species before, during, or after these steps, the stress in the anti-reflective layer may be avoided or compensated, and excessive LER or LWR may be avoided or reduced.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: February 23, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Tristan Ma
  • Patent number: 9257351
    Abstract: Cut spacer reference marks, targets having such cut spacer reference marks, and methods of making the same by forming spacer gratings around grating lines on a first layer, and fabricating a template mask that extends across and perpendicular to such spacer gratings. Cut spacer gratings are etched into a second layer using the template mask to superimpose at least a portion of the spacer gratings of the first layer into the second layer.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: February 9, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Christopher P. Ausschnitt, Nelson M. Felix, Scott S. Halle
  • Patent number: 9250532
    Abstract: There is provided a pattern forming method comprising: (i) a step of forming a first film on a substrate by using a first resin composition (I), (ii) a step of forming a second film on the first film by using a second resin composition (II) different from the resin composition (I), (iii) a step of exposing a multi-layered film having the first film and the second film, and (iv) a step of developing the first film and the second film in the exposed multi-layered film by using an organic solvent-containing developer to form a negative pattern.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: February 2, 2016
    Assignee: FUJIFILM Corporation
    Inventors: Keita Kato, Michihiro Shirakawa, Tadahiro Odani, Atsushi Nakamura, Hidenori Takahashi, Kaoru Iwato
  • Patent number: 9249013
    Abstract: Compositions for directed self-assembly patterning techniques are provided which avoid the need for separate anti-reflective coatings and brush neutral layers in the process. Methods for directed self-assembly are also provided in which a self-assembling material, such as a directed self-assembly block copolymer, can be applied directly to the silicon hardmask neutral layer and then self-assembled to form the desired pattern. Directed self-assembly patterned structures are also disclosed herein.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: February 2, 2016
    Assignee: Brewer Science Inc.
    Inventors: Yubao Wang, Mary Ann Hockey, Douglas J. Guerrero, Vandana Krishnamurthy, Robert C. Cox
  • Patent number: 9229328
    Abstract: A method of forming a semiconductor device structure comprises forming a template material over a substrate, the template material exhibiting preferential wetting to a polymer block of a block copolymer. A positive tone photoresist material is formed over the template material. The positive tone photoresist material is exposed to radiation to form photoexposed regions and non-photoexposed regions of the positive tone photoresist material. The non-photoexposed regions of the positive tone photoresist material are removed with a negative tone developer to form a pattern of photoresist features. The pattern of photoresist features and unprotected portions of the template material are exposed to an oxidizing plasma to form trimmed photoresist features and a pattern of template features. The trimmed photoresist features are removed with a positive tone developer. Other methods of forming a semiconductor device structure, and a semiconductor device structure are also described.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: January 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Ranjan Khurana, Gurpreet S. Lugani, Dan B. Millward
  • Patent number: 9229326
    Abstract: Provided is a method of forming a pattern for an integrated circuit. The method includes forming a first layer over a substrate, wherein the first layer's etch rate is sensitive to a radiation, such as an extreme ultraviolet (EUV) radiation or an electron beam (e-beam). The method further includes forming a resist layer over the first layer and exposing the resist layer to the radiation for patterning. During the exposure, various portions of the first layer change their etch rate in response to an energy dose of the radiation received therein. The method further includes developing the resist layer, etching the first layer, and etching the substrate to form a pattern. The radiation-sensitivity of the first layer serves to reduce critical dimension variance of the pattern.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shu-Hao Chang, Shinn-Sheng Yu, Jui-Ching Wu, Jeng-Horng Chen, Anthony Yen