Patents Examined by Kaushikkumar M Patel
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Patent number: 11226900Abstract: An approach for tracking data stored in caches uses a Bloom filter to reduce the number of addresses that need to be tracked by a coherence directory. When a requested address is determined to not be currently tracked by either the coherence directory or the Bloom filter, tracking of the address is initiated in the Bloom filter, but not in the coherence directory. Initiating tracking of the address in the Bloom filter includes setting hash bits in the Bloom filter so that subsequent requests for the address will “hit” the Bloom filter. When a requested address is determined to be tracked by the coherence directory, the Bloom filter is not used to track the address.Type: GrantFiled: January 29, 2020Date of Patent: January 18, 2022Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Weon Taek Na, Yasuko Eckert, Mark H. Oskin, Gabriel H. Loh, William Louie Walker, Michael Warren Boyer
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Patent number: 11210223Abstract: A storage device for outputting a program completion response before a program operation is completed includes a buffer memory for storing data from a host, a memory device for storing data from the buffer memory, and a memory controller for controlling the buffer memory and the memory device. The buffer memory stores the data according to mapping information. The memory controller includes a response controller for outputting a remapping request for changing mapping in the buffer memory, when the data and a storage request corresponding thereto are received, and outputting a storage completion response, when a remapping operation is completed, and a mapping controller for outputting, based on the remapping request, the mapping information on usable storage areas except an unusable area, by performing a remapping operation of changing an area in which the data is stored among the usable storage areas of the buffer memory to the unusable area.Type: GrantFiled: December 23, 2019Date of Patent: December 28, 2021Assignee: SK hynix Inc.Inventor: Sarath Kumar Kunnumpurathu Sivan
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Patent number: 11204700Abstract: A security extension design for non-volatile memory is shown. There is an in-system program loaded into the non-volatile memory. A memory controller downloads the in-system program to a data register to provide base firmware code, a function pointer structure and security firmware code on the data register. The memory controller executes the base firmware code, and security functions of the security firmware code are called by the base firmware code through information recorded in the function pointer structure and thereby the memory controller is switched to operate the non-volatile memory at a higher security level. The security firmware code uses an application programming interface (API) and is compatible with multiple projects.Type: GrantFiled: July 11, 2019Date of Patent: December 21, 2021Assignee: SILICON MOTION, INC.Inventors: Sung-Ling Hsu, Chih-Yu Lin, Hung-Ting Pan
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Patent number: 11194730Abstract: A method for depopulating data from cache includes receiving a command to depopulate the cache of selected data. The command has an application identifier as a parameter. The application identifier is associated with an application that previously accessed the data. The method searches the cache for data elements that are marked with the application identifier and removes the data elements from the cache. In certain embodiments, the data elements are marked with a first application identifier associated with an application that staged the data elements into the cache, and a second application identifier associated with an application that last accessed the data elements. In certain embodiments, removing the data elements from the cache comprises only removing the data elements from the cache if the application identifier matches one or more of the first application identifier and the second application identifier. A corresponding system and computer program product are also disclosed.Type: GrantFiled: February 9, 2020Date of Patent: December 7, 2021Assignee: International Business Machines CorporationInventors: Lokesh M. Gupta, Matthew G. Borlick, Kyler A. Anderson, Beth A. Peterson
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Patent number: 11182097Abstract: A computer-implemented method includes receiving a plurality of storage requests to store a plurality of objects in a dispersed storage network. The computer-implemented method further includes transforming each object in the plurality of objects into a set of error encoded slices. The computer-implemented method further includes dispersing each error encoded slice in each set of error encoded slices to a memory zone of a distinct storage unit. The computer-implemented method further includes co-locating two or more error encoded slices in a common memory zone of a storage unit based, at least in part, on an expiry time associated with the two or more encoded slices. The computer-implemented method further includes logically deleting the common memory zone of the storage unit after all error encoded slices stored in the common memory zone have expired.Type: GrantFiled: May 14, 2019Date of Patent: November 23, 2021Assignee: International Business Machines CorporationInventors: Praveen Viraraghavan, Ethan Wozniak, Amit Lamba
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Patent number: 11176052Abstract: A method for improving cache hit ratios for selected volumes within a storage system is disclosed. In one embodiment, such a method includes storing, in a cache of a storage system, non-favored storage elements and favored storage elements. The favored storage elements are retained in the cache longer than the non-favored storage elements. The method maintains a “non-favored” LRU list that contains entries associated with non-favored storage elements and designates an order in which the non-favored storage elements are evicted from the cache. The method also maintains one or more “favored” LRU lists that contain entries associated with favored storage elements and designate an order in which the favored storage elements are evicted from the cache. Each “favored” LRU list is associated with favored storage elements that have a different preferred residency time in the cache. A corresponding system and computer program product are also disclosed.Type: GrantFiled: May 12, 2019Date of Patent: November 16, 2021Assignee: International Business Machines CorporationInventors: Lokesh M. Gupta, Kevin J. Ash, Beth A. Peterson, Kyler A. Anderson
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Patent number: 11163464Abstract: Techniques for storage management involve: acquiring capacities of a plurality of disks configured to provide redundant storage; determining, based on the capacities of the plurality of disks, a first total capacity corresponding to a first candidate scheme of the redundant storage and a second total capacity corresponding to a second candidate scheme of the redundant storage, all of the plurality of disks being used in the first candidate scheme, and a part of the plurality of disks being used in the second candidate scheme; and determining a target scheme of the redundant storage from the first candidate scheme and the second candidate scheme based on the first total capacity and the second total capacity. Accordingly, an optimal disk configuration scheme can be selected to generate an optimal disk group, so as to improve storage capability and storage management efficiency.Type: GrantFiled: August 11, 2020Date of Patent: November 2, 2021Assignee: EMC IP Holding Company LLCInventors: Jian Gao, Rongrong Shang
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Patent number: 11150832Abstract: The present disclosure relates to a method, a device and a computer program product for backup management. An initial set of data items associated with a plurality of historical data backup operations are obtained, a data item in the initial set of data items indicates a data amount and time consumption associated with a corresponding historical data backup operation. A degree of change in time consumption per unit data amount of a candidate data item in the initial set of data items is determined and the candidate data item from the initial set of data items is removed based on the degree of change to generate a reference set of data items, which is stored for predicting time consumption of a future data backup operation.Type: GrantFiled: September 27, 2019Date of Patent: October 19, 2021Assignee: EMC IP HOLDING COMPANY LLCInventors: Andy Ke, Rita Li
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Patent number: 11144219Abstract: Techniques for ensuring sufficient available storage capacity for data resynchronization or data reconstruction in a cluster of a hyper-converged infrastructure (HCI) deployment are provided. In one set of embodiments, a computer system can receive a request to provision or reconfigure an object on the cluster. The computer system can further calculate one or more storage capacity reservations for one or more host systems in the cluster, where the one or more storage capacity reservations indicate one or more amounts of local storage capacity to reserve on the one or more host systems respectively in order to ensure successful data resynchronization or data reconstruction in the case of a host system failure or maintenance event. If placement of the object on the cluster will result in a conflict with the one or more storage capacity reservations, the computer system can deny the request to provision or reconfigure the object.Type: GrantFiled: August 23, 2019Date of Patent: October 12, 2021Assignee: VMware, Inc.Inventors: Duncan Epping, Cormac Hogan, Frank Denneman
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Patent number: 11144236Abstract: A method includes: executing a first process includes receiving an entry that includes a kay and a value, selecting a first list from among a plurality of lists in accordance with a first hash value, adding, to the selected first list, a first identifier in association with the received entry, and storing the received entry in any of a first memory device and a second memory device that is greater in latency than the first memory device; and executing a second process that includes receiving a searching request for a value, selecting the first list based on the first hash value derived from the searching key in the received searching request, obtaining the first identifier from the first list selected in the second process, obtaining the entry associated with the first identifier obtained in the second process, and outputting the value in the entry obtained in the second process.Type: GrantFiled: July 12, 2019Date of Patent: October 12, 2021Assignee: FUJITSU LIMITEDInventor: Shun Gokita
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Patent number: 11093400Abstract: Novel techniques are described for lock-free sharing of a circular buffer. Embodiments can provide shared, lock-free, constant-bitrate access by multiple consumer systems to a live stream of audiovisual information being recorded to a circular buffer by a producer. For example, when a producer system writes a data stream to the circular buffer, the producer system records shared metadata. When a consumer system desires to begin reading from the shared buffer at a particular time, the shared metadata is used to compute a predicted write pointer location and corresponding dirty region around the write pointer at the desired read time. A read pointer of the consumer system can be set to avoid the dirty region, thereby permitting read access to a stable region of the circular buffer without relying on a buffer lock.Type: GrantFiled: December 9, 2019Date of Patent: August 17, 2021Assignee: Sling Media Pvt. Ltd.Inventors: Amit Kumar, Gopikumar Ranganathan
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Patent number: 11093415Abstract: A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.Type: GrantFiled: March 29, 2019Date of Patent: August 17, 2021Assignee: MARVELL ASIA PTE, LTD.Inventors: Enrique Musoll, Tsahi Daniel
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Patent number: 11086523Abstract: In a hierarchical storage system, blocks of data selected for auto-tiering migration, are selected based on dynamically adjusted group sizes. Contiguous blocks are organized into default groups. I/O activity of the blocks in a group is monitored. Based on the I/O activity, the default groups may be sub-divided into smaller sub-groups or combined into larger groups, to separate as much as practical, contiguous series of cooler blocks and contiguous series of hotter blocks into respective focused (concentrated) groups or sub-groups. The concentrated group or sub-group may then be migrated according to the average I/O activity of the included blocks. Group configurations are continually and dynamically adjusted according to changing I/O conditions.Type: GrantFiled: January 3, 2020Date of Patent: August 10, 2021Assignee: International Business Machines CorporationInventors: Yongjie Gong, Shuang Shuang Li, Yang Liu, Mei Mei, Xue Qiang Zhou
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Patent number: 11080190Abstract: Embodiments of the present disclosure relate to an apparatus comprising a memory and at least one processor. The at least one processor is configured to monitor one or more processing threads of a storage device. Each of the one or more processing threads includes two or more cache states. The at least one processor also updates one or more data structures to indicate a subject cache state of each of the one or more processing threads and detect an event that disrupts at least one of the one or more processing threads. Further, the processor determines a cache state of the at least one of the one or more processing threads contemporaneous to the disruption event using the one or more data structures and performs a recovery process for the disrupted at least one of the one or more processing threads.Type: GrantFiled: July 10, 2019Date of Patent: August 3, 2021Assignee: EMC IP Holding Company LLCInventors: Kaustubh Sahasrabudhe, Steven Ivester
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Method and apparatus for performing atomic operations on local cache slots of a shared global memory
Patent number: 11074113Abstract: A storage system includes at least two independent storage engines interconnected by a fabric, each storage engine having two compute nodes. A shared global memory is implemented using cache slots of each of the compute nodes. Memory access operations to the slots of shared global memory are managed by a fabric adapter to guarantee that the operations are atomic. To enable local cache operations to be managed independent of the fabric adapter, a cache metadata data structure includes a global flag bit for each cache slot, that is used to designate the cache slot as globally available or temporarily reserved for local IO processing. The cache metadata data structure also includes a mutex (Peterson lock) for each cache slot to enforce a mutual exclusion concurrency control policy on the cache slot between the two compute nodes of the storage engine when the cache slot is used for local IO processing.Type: GrantFiled: May 21, 2020Date of Patent: July 27, 2021Assignee: EMC IP Holding Company LLCInventors: Steven Ivester, Kaustubh Sahasrabudhe -
Patent number: 11074187Abstract: Techniques manage addresses in a storage system. In such techniques, an address page of an address pointing to target data in the storage system is determined in response to receiving an access request for accessing data in the storage system. A transaction for managing the address page is generated on the basis of the address page, here the transaction at least comprises an indicator of the address page and a state of the transaction. A counter describing how many times the address page is referenced is set. The transaction is executed at a control node of the storage system on the basis of the counter. With such techniques, the access speed for addresses in the storage system can be accelerated, and then the overall response speed of the storage system can be increased.Type: GrantFiled: March 15, 2019Date of Patent: July 27, 2021Assignee: EMC IP Holding Company LLCInventors: Geng Han, Jian Gao, Lifeng Yang, Xinlei Xu, Yousheng Liu
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Patent number: 11061595Abstract: A method of writing to a data storage drive having a first media partition having a first write speed and a second media partition having a second write speed slower than the first write speed includes mapping a plurality of logical block addresses (LBAs) to a plurality of physical block addresses (PBAs) of the first media partition, and writing to the plurality of LBAs mapped to the PBAs of the first media partition. It is determined whether the first media partition is at or above a predetermined storage level, and, when the first media partition is at or above the predetermined storage level, data is moved moving data from the first media partition to a plurality of PBAs in the second media partition, and mapping of LBAs and PBAs in the data storage device is updated.Type: GrantFiled: May 10, 2019Date of Patent: July 13, 2021Assignee: Seagate Technology LLCInventor: JinQuan Shen
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Patent number: 11061780Abstract: Applying machine-learning to optimize the operational efficiency of data backup systems is described. A machine-learning system creates a training set of multiple features for each of multiple historical data backup jobs. The machine-learning system trains a prediction model to predict, based on the training set, the probabilities that the corresponding historical data backup jobs failed during the next historical data backup window. The machine-learning system creates an operational set of multiple features for each of multiple scheduled data backup jobs. The trained prediction model predicts, based on the operational set, the probabilities that the corresponding scheduled data backup jobs will fail during the next scheduled data backup window. The predicted probability that a scheduled data backup job will fail during the next scheduled data backup window is output, thereby enabling an operator to remediate the scheduled data backup job prior to the next scheduled data backup window.Type: GrantFiled: October 8, 2019Date of Patent: July 13, 2021Assignee: EMC IP Holding Company LLCInventors: Peter Marelas, Aruna Kolluru
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Patent number: 11036425Abstract: A storage device includes a main storage and a storage controller to control the main storage. The main storage stores data and includes a plurality of nonvolatile memory devices. The storage controller loads at least one of (a) at least a portion of mapping tables and (b) at least one of a portion of directories to a host memory buffer included in an external host device, based on at least one of a size of the host memory buffer and locality information associated with a data access pattern of the host device. The mapping tables are stored in the nonvolatile memory devices and the mapping tables indicate a mapping relationship between a physical address and a logical address of corresponding ones of the nonvolatile memory devices. The directories store address information of the mapping tables.Type: GrantFiled: July 9, 2019Date of Patent: June 15, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Su-Ryun Lee, Bum-Hee Lee
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Patent number: 11036398Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.Type: GrantFiled: August 8, 2019Date of Patent: June 15, 2021Assignee: Rambus, Inc.Inventors: Aws Shallal, Michael Miller, Stephen Horn