Abstract: Apparatuses, methods, and systems are described herein for a thermal distribution manager to allocate multiple data portions of a data object to be written into a plurality of memory devices, as well as to restore the data object. The thermal distribution manager also reads some of the allocated multiple data portions from the respective memory devices. The allocation may include division of the data object and is based at least in part on respective temperatures of the memory devices prior to a write time and the reading and restoration is based at least in part on respective temperatures of the memory devices prior to a read time. The thermal distribution manager may allocate the multiple data portions according to a frequency of access of a first data portion relative to a frequency of access of a second data portion. Additional embodiments may be described and claimed.

Abstract: An information processing system includes a first device and a second device that is configured to perform a short-range wireless communication with the first device. In a case where the first device requests an external authentication apparatus for authentication, the first device sends information regarding the second device to the external authentication apparatus.

Abstract: A system for performing auto-tiering is disclosed. The system may include a plurality of storage devices offering a plurality of resources and organized into storage tiers. The storage devices may store data for virtual machines. A receiver may receive I/O commands and performance data for the virtual machines. A transmitter may transmit responses to the I/O commands. An auto-tiering controller may select storage tiers to store the data for the virtual machines and may migrate data between storage tiers responsive to the performance data. The selection of the storage tiers may optimize the performance of all virtual machines across all storage tiers, factoring the change in performance of the virtual machines and a migration cost to migrate data between storage tiers.

Abstract: Technologies for least recently used (LRU) cache replacement include a computing device with a processor with vector instruction support. The computing device retrieves a bucket of an associative cache from memory that includes multiple entries arranged from front to back. The bucket may be a 256-bit array including eight 32-bit entries. For lookups, a matching entry is located at a position in the bucket. The computing device executes a vector permutation processor instruction that moves the matching entry to the front of the bucket while preserving the order of other entries of the bucket. For insertion, an inserted entry is written at the back of the bucket. The computing device executes a vector permutation processor instruction that moves the inserted entry to the front of the bucket while preserving the order of other entries. The permuted bucket is stored to the memory. Other embodiments are described and claimed.

Abstract: Computer system and method for managing storage requests in a distributed storage system uses congestion data related to processing of storage requests for local storage to adaptively adjust a bandwidth limit for a first class of storage requests to be processed. The bandwidth limit is enforced on the storage requests belonging to the first class of storage requests without enforcing any bandwidth limit on the storage requests belonging to a second class of storage requests.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine one or more memory channels of a plurality of memory channels to be enabled based on an indication received from a basic input/output system (BIOS), determine whether a number of the one or more memory channels to be enabled is greater than a maximum number of memory channels permitted, cause a platform reset if the number of the one or more memory channels is greater than the maximum number of memory channels, and permit enablement of the one or more memory channels if the number of the one or more memory channels is not greater than the maximum number of memory channels.

Abstract: Systems and methods for writing data are provided. A lock-free container and methods of writing to the lock-free container are disclosed. The container is associated with a tail pointer that identifies free space in the container. Threads writing to the container access the tail pointer and update an offset in the tail pointer to account for a size of a write to the container. Multiple threads can write to the same container without having to contend for a container lock.

Abstract: A system and method for storage system property deviation are provided. In one embodiment, a storage system is presented comprising a memory and a controller configured to: receive a request from a host to modify a write parameter used to write data to the memory; write data to the memory using the modified write parameter; restore the write parameter to its pre-modified state; and re-write the data to the memory in a background operation using the write parameter in its pre-modified state. Other embodiments are provided.

Abstract: A flash device access method, apparatus, and system, where a flash device includes a controller and a storage array. The method includes dividing the storage array into a specific storage unit and a user storage unit, such that a storage feature of the specific storage unit is the same as that of the user storage unit, writing, by the controller, specific data into the specific storage unit, reading, by the controller, the specific data stored in the specific storage unit, determining, by the controller, a decision voltage (Vread) based on the read specific data, and reading, by the controller using the determined Vread, the user data stored in the user storage unit. Hence, incorrect determining of the data stored in the flash device may be reduced using the access method, apparatus, and system.

Abstract: A computing system includes a first storage unit at a first computing site. The first storage unit stores units of work data and data synchronously replicated from a first server cluster of a second computing site. The system further includes a second server cluster at the first computing site, the second server cluster is a proxy node of the first server cluster. The system further includes a second storage unit at the first computing site, the second storage unit stores the units of work data and data from the first storage unit asynchronously into the second storage unit. The system further includes a third server cluster at the first computing site, the third server cluster processes the units of work data asynchronously replicated into the second storage unit.

Abstract: A computer-implemented method according to one embodiment includes receiving, at a storage system, a request to allocate persistent data storage for use by a container within an orchestration system, where the request includes an orchestration system identifier, selecting a storage volume within the storage system for use by the container within the orchestration system, determining a storage identifier for the storage volume within the storage system, and storing, within the storage system, an association between the orchestration system identifier and the storage identifier.

Abstract: A method may include: partitioning data on an on-chip and/or an off-chip storage medium into different data blocks according to a pre-determined data partitioning principle, wherein data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block; and a data indexing step for successively loading different data blocks to at least one on-chip processing unit according a pre-determined ordinal relation of a replacement policy, wherein the repeated data in a loaded data block being subjected to on-chip repetitive addressing. Data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block, and the data partitioned into the same data block can be loaded on a chip once for storage, and is then used as many times as possible, so that the access is more efficient.

Abstract: A method, non-transitory computer readable medium, and device that assists with performing global data deduplication on data blocks across different volumes includes identifying at least two data blocks stored in two or more storage volumes. It is determined whether the at least two data blocks are classified as a shared data block. A new data volume signature is created when the at least two data blocks are determined to be shared. One of the at least two data blocks that are determined to be shared is deleted and the other one of the at least two data blocks and the created signature in one of the two or more storage volumes is stored.

Abstract: Provided are techniques for fast cache demotions in storage controllers with metadata. A track in a demotion structure is selected. In response to determining that the track in the demotion structure does not have invalidate metadata set, demoting the track from cache. In response to determining that the track has invalidate metadata set, the track is moved from the demotion structure to an invalidate metadata structure. One or more tasks are created to process the invalidate metadata structure, wherein each of the one or more tasks selects a different track in the invalidate metadata structure, invalidates metadata for that track, and demotes that track.

Abstract: Snapshot Isolation (SI) is an established model in the database community, which permits write-read conflicts to pass and aborts transactions only on write-write conflicts. With the Write Skew Anomaly (WSA) correctly eliminated, SI can reduce the occurrence of aborts, save the work done by transactions, and greatly benefit long transactions involving complex data structures. Embodiments include a multi-versioned memory subsystem for hardware-based transactional memory (HTM) on the GPU, with a method for eliminating the WSA on the fly, and incorporates SI. The GPU HTM can provide reduced compute time for some compute tasks.

Abstract: A method for utilizing parallel paths of differing performance to improve efficiency is disclosed. In one embodiment, such a method includes transmitting, over a faster path, a first command to perform first actions intended to improve efficiency of second actions associated with a second command. The method transmits, over a slower path in parallel with the faster path, the second command. Alternatively, a method for utilizing parallel paths of differing performance to improve efficiency includes receiving, over a faster path, a first command to perform first actions intended to improve efficiency of second actions associated with a second command. The method executes the first command to perform the first actions. The method receives, over a slower path in parallel with the faster path, the second command and executes the second command to perform the second actions. Corresponding systems and computer program products are also disclosed.

Abstract: In one embodiment, a method includes selectively invalidating data stored in at least one cache line of a cache memory in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed. The predetermined amount of time is shorter than a round-trip time to process a plurality of blocks of data stored sequentially to a ring buffer. In other embodiments, methods, systems, and computer program products are described for efficient use of cache memory using an expiration timer.

Abstract: A memory device, includes a non-volatile semiconductor memory including a plurality of first areas, each corresponding to an erasing unit, each of the first areas including a plurality of second areas, each corresponding to a writing unit; and a controller circuitry configured to erase data stored in a first area of the non-volatile semiconductor memory, track amount of time elapsed since the erasing data from the first area, write first data into one or more unwritten second areas of the first area before the tracked amount of time reaches a particular time period, and write second data into one or more unwritten second areas of the first area in response to the tracked amount of time reaching the particular time period, each of the writing of the first data and the writing of the second data being carried out independently of an instruction from a host.

Abstract: A hardware system for data conversion, comprising: a space searching circuit, for searching space characters in a data stream of original data after receiving an instruction sent by a server to read and write data; a length detecting circuit, for detecting a length of data in the data stream of original data according to two adjacent space characters; a parallel encoding circuit, for converting the original data according to the data format in the instruction according to the length and the data stream of original data and outputting the converted data. The hardware system for data conversion is embedded in a storage device. The entire data conversion process could not only improve the efficiency of data conversion, but also does not occupy the resources of the CPU and DRAM of the server or the MCU of the SSD controller.

Abstract: A device includes a schedule engine including a mode selection input. The schedule engine has an operating mode based on the mode selection input. The operating mode includes an opportunistic scheduling mode based on the mode selection input having a first value and a pipelined scheduling mode based on the mode selection input having a second value. The device further includes a buffer coupled to the schedule engine.