Abstract: A memory device is configured to communicate with one or more external devices, the memory device including a configurable bit or a mode select pin for determining which one of two or more different communication protocols that the memory device uses to communicate with the one or more external devices, wherein the two or more different communications protocols include at least a Controller Area Network (CAN) protocol and a System Management Bus (SMBus) protocol.

Abstract: A storage system comprises multiple storage nodes each comprising at least one storage device. Each of the storage nodes further comprises a set of processing modules configured to communicate over one or more networks with corresponding sets of processing modules on other ones of the storage nodes. The sets of processing modules of the storage nodes each comprise at least one data module and at least one control module. The storage system is configured to assign portions of a content-based signature space of the storage system to respective ones of the data modules, and to assign portions of a logical address space of the storage system to respective ones of the control modules. The assignment of portions of the logical address space to the control modules is configured to at least partially offset an unbalanced condition between local physical storage capacities of the data modules.

Abstract: A pre-fetching technique determines what data, if any, to pre-fetch on a per-logical storage unit basis. For a given logical storage unit, what, if any, data to prefetch is based at least in part on a collective sequential proximity of the most recently requested pages of the logical storage unit. Determining what, if any, data to pre-fetch for a logical storage unit may include determining a value for a proximity metric indicative of the collective sequential proximity of the most recently requested pages, comparing the value to a predetermined proximity threshold value, and determining whether to pre-fetch one or more pages of the logical storage unit based on the result of the comparison. A data structure may be maintained that includes most recently requested pages for one or more logical storage units. This data structure may be a table.

Abstract: An offset can be determined based on a characteristic of a memory system associated with a system block. The system block corresponds to logical blocks. A first group of physical blocks of the memory system can be assigned to a group of the plurality of logical blocks of the system block. A second group of physical blocks of the memory system can be identified at a location that is based on the offset and the first group of physical blocks. Furthermore, the second group of physical blocks of the memory system can be assigned to another group of the plurality of logical blocks associated with the system block. Data can be stored by using the system block with the first group and second group of physical blocks.

Abstract: An apparatus includes a first processor to execute a user-level application to operate in a virtual address, and a co-processor to execute a computing kernel associated with user-level application elements to be performed on the co-processor. The computing kernel is to operate in the virtual address. A memory includes physical addresses, and a partition used to map the virtual address associated with the first processor and to map the virtual address associated with the co-processor. A packet processor manages communications between the first processor and the co-processor. The packet processor receives packets from the first processor, with the packets including memory addresses identifying code and data of the computing kernel. The packet processor stores the packets in a queue associated with the user-level application, and outputs the packets to the co-processor, such that the co-processor is enabled to execute the computing kernel.

Abstract: Embodiments disclosed herein provide a domain aware data migration scheme between processing elements, memory, and various caches in a CC-NUMA system. The scheme creates domain awareness in data migration operations, such as Direct Cache Transfer (DCT) operation, stashing operation, and in the allocation of policies of snoop filters and private, shared, or inline caches. The scheme defines a hardware-software interface to communicate locality information (also referred herein as affinity information or proximity information) and subsequent hardware behavior for optimal data migration, thus overcoming traditional CC-NUMA limitations.

Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request. The processing unit performing the processing may proceed with processing of the restrained storage operand request, without performing the suppressing, where the processing can be accomplished using cache private to the processing unit. Otherwise the suppressing may continue until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.

Abstract: An information processing apparatus includes: a processor that: compares first and second identification information, wherein the first identification information identifies a storage medium in which apparatus information about the information processing apparatus is saved, the apparatus information is memorized in a main board of the information processing apparatus, and the second identification information identifies a storage medium connected to the information processing apparatus; detects that a save destination of the apparatus information is replaced when the first and second identification information do not coincide with each other; and determines a state of the save destination of the apparatus information in accordance with a storage state of the apparatus information in the connected storage medium and a storage state of the apparatus information in the main board of the information processing apparatus when the first and second identification information coincide with each other.

Abstract: A memory system includes a nonvolatile memory device; and a controller configured to receive an operation command for a target logical address from a host device, and control the nonvolatile memory device in response to the operation command, wherein the controller determines a target logical address range including the target logical address among a plurality of logical address ranges, and determines whether the target logical address has a sequential attribute, based on a target count corresponding to the target logical address range among counts corresponding to the plurality of logical address ranges.

Abstract: Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the techniques include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. The techniques also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. The techniques include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.

Abstract: A method for managing backups includes receiving, via a first backup stream, first data associated with a first tagged backup stripe, wherein the first tagged backup stripe is associated with a first routing tag, directing, based on the first routing tag, the first data to a first backup instance, receiving, via a second backup stream, second data associated with a second tagged backup stripe, wherein the second tagged backup stripe is associated with the first routing tag, directing, based on the first routing tag, the second data to the first backup instance, and performing, in the first backup instance, a deduplication operation on the first data and the second data.

Abstract: Systems, apparatuses and methods may provide for technology that detects, by a current stage of a hardware pipeline, a flush request with respect to a first resource and executes, by the current stage, one or more transactions associated with a second resource. Additionally, the current stage may conduct one or more flush operations with respect to the first resource, wherein the one or more transactions associated with the second resource are executed after detection of the flush request and before the one or more flush operations.

Abstract: The disclosed computer-implemented method includes receiving an indication that cache data is to be copied from an originating cluster having a specified number of replica nodes to a destination cluster having an arbitrary number of replica nodes. The method further includes copying the cache data to a cache dump and creating a log that identifies where the cache data is stored in the cache dump. The method further includes copying the cache data from the cache dump to the replica nodes of the destination cluster. The copying includes writing the copied data in a distributed manner, such that at least a portion of the copied data is distributed over each of the replica nodes in the destination cluster. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A semiconductor memory module includes data buffers that exchange first data signals with an external device, nonvolatile memory devices that are respectively connected to the data buffers through data lines, and a controller connected to the data lines. The controller receives an address, a command, and a control signal from the external device, and depending on the address, the command, and the control signal, the controller controls the data buffers through first control lines and controls the nonvolatile memory devices through second control lines.

Abstract: A RAID controller may update a RAID array by receiving updated data for a first data strip in a set of data strips in the RAID array. The RAID controller may then determine that the first data strip is stored on a device that is experiencing a slow condition. The RAID controller may then force, based on the determining, a promoted stripe write.

Abstract: Techniques are described for performing a read scan process on a non-volatile memory system in order to determine memory blocks that may have a high bit error rate, where if such blocks are found they can be refreshed. Rather than work through the blocks of a memory system sequentially based on the physical block addresses, the memory system maintains a measure of data quality, such as an estimated or average bit error rate, for multi-block groups. For example, the groups can correspond to regions of memory die in the system. The groups are ranked by their data quality, with the groups being scanned in order of the data quality. The blocks within a group can also be ranked, based on factors such as the program/erase count.

Abstract: A memory system may include: a plurality of resources; and a frequency adjuster configured to adjust operating frequencies of the plurality of resources at a predetermined adjustment timing, wherein the adjustment timing comprises at least one timing for dividing partial operation periods of at least one resource among the plurality of resources.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory including a plurality of blocks, and a controller. The controller receives from the host information indicative of the total number of processes running on the host. The controller executes processing of moving data stored in at least one block of the nonvolatile memory to at least one block of the other blocks of the nonvolatile memory, after determining that the total number of processes exceeds a first threshold value.

Abstract: A method of processing in-memory commands in a high-bandwidth memory (HBM) system includes sending a function-in-HBM instruction to the HBM by a HBM memory controller of a GPU. A logic component of the HBM receives the FIM instruction and coordinates the instructions execution using the controller, an ALU, and a SRAM located on the logic component.

Abstract: An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level. The memory controller having early demotion logic circuitry to demote a page from the higher level to the lower level without system software having to instruct the memory controller to demote the page and before the system software promotes another page from the lower level to the higher level.