Abstract: Provided is a semiconductor memory device in which SRAM has a construction such that an nMOS transistor formation region and a pMOS transistor formation region are disposed in a direction along which a bit line extends, thereby reducing delay in the bit line caused by wiring parasitic capacity. A main word line has a shape such that the main word line is disposed every two memory cell rows avoiding a bit line contact and part of the main word line extends to the row adjacent to the two rows. Accordingly, the main word line can be easily formed in the layer below the bit lines. In the bit lines, wiring parasitic capacity between the main word line and the bit line is reduced and therefore delay in the bit line is eliminated. As a result, time delay in memory operation is reduced.

Abstract: A semiconductor device for manufacturing a semiconductor memory cell includes the steps of: a) preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs; b) forming a supporting layer, made of carbon, on top of the active matrix and patterned into a predetermined configuration, thereby obtaining a patterned supporting layer; c) forming bottom electrodes on the patterned supporting layer; and d) removing the patterned supporting layer.

Abstract: A fabrication process for a thin film transistor including, in the first process step, performing semiconductor layer formation processing, crystallization processing, and first gate insulator formation processing without exposing the substrate to atmosphere. In the second process step, performing rapid thermal processing of the first gate insulator layer and the semiconductor layer. In the third process step, performing patterning of the first gate insulator layer and the semiconductor layer. In the fourth process step, performing cleaning by etching the surface of the first gate insulator layer which has been contaminated by the resist mask. In the fifth process step, performing hydrogenation processing followed by formation of the second gate insulator layer on the surface of the first gate insulator layer.

Abstract: An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n+/n−/p−/n−/n+ regions. The emitter is formed of the second N+ region and the second N− well. The parasitic base is formed by the p− substrate or well. The collector is formed of the first well and the first n+ region. The benefit of the first embodiment is the trigger voltage is lower because the junction between the n− well (emitter) and P− substrate (base) and the junction between P− substrate (base) and the n− well have lower cross over concentrations. The second embodiment is similar to the first embodiment with the addition of the first gate. The first gate is preferably connected to the first n+ region and the Vpad. The third embodiment contains the same elements as the second embodiment with the addition of a third n+ region.

Abstract: A semiconductor device having a retrograde channel profile is achieved by forming a retrograde impurity region in the surface portion of a semiconductor substrate, and subsequently forming a semiconductor layer on the retrograde impurity region at a predetermined thickness. The thickness of the semiconductor layer is controlled to localize the retrograde impurity region and its impurity concentration peak at a predetermined depth, thereby reducing the device's susceptibility to “reverse short channel effects.

Abstract: An object of the invention is reducing a manufacturing cost of an EL display device and an electronic device equipped therewith. In an active matrix type EL display device, an EL material for a pixel portion is formed by coating steps using a dispenser device. As a discharge port of the dispenser is made into a linear shape, the throughput is increased. Such the dispenser device is used, so that it is possible to simplify the EL layer forming steps, then, to reduce the manufacturing cost.

Abstract: The present invention relates to a thin film transistor and a fabricating method thereof wherein a source/drain region and a gate electrode are formed in the same layer, which improves the degree of planarization. Because source/drain electrodes and a gate electrode are formed by patterning the same layer with a single mask, the invention reduces the number of fabrication steps. The TFT includes an insulated substrate which is transparent, a source electrode and a drain electrode on the insulated substrate. The source and drain electrodes are separated each other, and a gate electrode is between the source and drain electrodes on the insulated substrate. A gate insulating layer covers the source and drain electrodes and the gate electrodes on the gate insulating layer. An active layer is then formed on the gate insulating layer. Source and drain regions are formed at each end of the active layer corresponding to the gate electrode and a channel region is formed between the source and drain regions.

Abstract: Annular and linear contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

Abstract: A method of patterning conductive lines (252) of a memory array integrated circuit (200) using a hard mask (244) and reactive ion etching (RIE). Using a hard mask (244) prevents oxidation of underlying conductive lines (210).

Abstract: A method for processing a substrate comprising the formation of a metal nitride/metal stack suitable for use as a barrier/liner for sub-0.18 &mgr;m device fabrication. After a metal nitride layer is deposited upon a metal layer, the metal nitride layer is exposed to a treatment step in a nitrogen-containing environment, e.g., a plasma. The plasma treatment modifies the entire metal nitride layer and a top portion of the underlying metal layer. The plasma adds nitrogen to the top portion of the metal layer, resulting in the formation of a nitrated-metal layer. Aside from reducing the microstructure mismatch across the nitride-metal interface, the plasma treatment also densifies and reduces impurities from the deposited nitride layer. The resulting nitride/metal stack exhibits improved film properties, including enhanced adhesion and barrier characteristics. A composite nitride layer of a desired thickness can also be formed by repeating the deposition and treatment cycles of thinner component nitride layers.

Abstract: A system and method for efficiently interconnecting a plurality of ICs, thereby improving the electrical performance of the overall system while reducing contact degradation due to stress that results from differences in the coefficients of thermal expansion of the various components during thermal cycling

Abstract: A method for making a microstructure assembly, the method including the steps of providing a first substrate and a second substrate; depositing an electrically conductive material on the second substrate; contacting the second substrate carrying the electrically conductive material with the first substrate; and then supplying current to the electrically conductive material to locally elevate the temperature of said electrically conductive material and cause formation of a bond between the first substrate and the second substrate.

Abstract: A surface acoustic wave device includes a surface acoustic wave element and a package. The package has a base member and a conductive cap member which are joined together by a sealing material so as to hermetically seal the surface acoustic wave element therein. The conductive cap member is coated with the sealing material on the entire surface thereof that is disposed opposite to the base member.

Abstract: The present disclosure pertains to the discovery that TiN films having a thickness of greater than about 400 Å and, particularly greater than 1000 Å, and a resistivity of less than about 175 &mgr;&OHgr;cm, can be produced by a CVD technique in which a series of TiN layers are deposited to form a desired TiN film thickness. Each layer is deposited employing a CVD deposition/treatment step. During a treatment step, residual halogen (typically chlorine) was removed from the CVD deposited film. Specifically, a TiN film having a thickness of greater than about 400 Å was prepared by a multi deposition/treatment step process where individual TiN layers having a thickness of less than 400 Å were produced in series to provide a finished TiN layer having a combined desired thickness. Each individual TiN layer was CVD deposited and then treated by exposing the TiN surface to ammonia in an annealing step carried out in an ammonia ambient.

Abstract: The invention relates to a semiconductor device (100) with a semiconductor body (10) comprising at least one semiconductor element (H) with an active area (A) and a coil (20) coupled to said element (H). The coil (20) and a further coil (21) jointly form a transformer (F). The semiconductor body (10) is secured to a carrier plate (30) which comprises an electrically insulating material and is covered with a conductor track (21). According to the invention, the further coil (21) is positioned on the carrier plate (30) and is formed by the conductor track (21) and electrically separated from the coil (20). In this way, a-device (100) is obtained which is easier to manufacture than the known device. Moreover, the communication between the element (H) and the outside world does not involve an electrical coupling and hence, for example, bonding wires, are not necessary. The invention is particularly advantageous for a (discrete) bipolar transistor, which can suitably be used for surface mounting.

Abstract: A semiconductor device of the present invention includes an electrode, which is formed over a substrate and contains ruthenium. Crystal grains of ruthenium in the electrode have stepped surfaces.

Abstract: A film-forming apparatus for forming a non-single crystalline silicon series semiconductor film on a substrate in a film-forming space provided in a vacuum chamber using a very high frequency power supplied through a high frequency power supply means comprising a bar-like shaped electrode, wherein said bar-like shaped electrode is arranged such that the longitudinal direction thereof intersects a direction for said substrate to be moved, and a length of said film-forming space relative to the direction for said substrate to be moved is in a range of from {fraction (1/16)} to ½ of a wavelength of said very high frequency power supplied in said film-forming space. A film-forming method for forming a non-single crystalline silicon series semiconductor film on a substrate using said film-forming apparatus.

Abstract: An ion generator generates ions above a semiconductor wafer and the ions are directed towards a surface of a semiconductor wafer. The ions combine with static charges on the semiconductor wafer to thereby discharge the surface of the semiconductor wafer.

Abstract: The present invention provides a method of manufacturing an interconnect structure within a substrate. The method includes forming an opening in a substrate, which may be a dielectric layer having a low k; for example, one where the dielectric constant ranges from about 3.9 to about 1.9. This method further includes forming a passivation layer within the opening and a photoresist within the opening and over the passivation layer. The passivation layer substantially or completely inhibits the diffusion of elements from the substrate that can deactivate a photo acid generator (PAG) within the photoresist, which prevents the photoresist from developing properly.

Abstract: An ONO dielectric layer is formed on the surface of a substrate, and then a plurality of bit lines are formed in the substrate by utilizing a photolithography and an ion implantation process. Thereafter the ONO dielectric layer in the periphery area is removed and the threshold voltage of the periphery transistor is adjusted. After the ONO dielectric layer in the read only memory area is removed, and a buried drain oxide layer and a plurality of gate oxide layers are formed atop each bit line and the surface of each device respectively. Then each word line in the memory area and each gate of each periphery transistor in the periphery area is formed so as to simultaneously form at least a nitride read only memory in the nitride read only memory area and a high, low threshold voltage device in the read only memory area. Finally the threshold voltage of the high threshold voltage device is adjusted by utilizing a ROM code implantation process.