Abstract: A process to fabricate a thin film transistor using an intrinsic polycrystalline silicon film, by a method of: preparing a semiconductor assembly; forming an insulation layer on a substrate; forming a first amorphous silicon layer on said insulation layer; forming silicon nucleation sites on said first amorphous silicon layer; converting said first amorphous silicon layer into hemispherical grained silicon, said hemispherical grained silicon being formed about said silicon nucleation sites; forming a second amorphous silicon layer covering said hemispherical grained silicon; annealing said second amorphous silicon layer to convert said second amorphous silicon layer into a grained silicon film, said grained silicon film being formed about said hemispherical grained silicon and having a dimension of approximately 0.1 microns to 0.

Abstract: The present invention concerns an optical component having at least one guide with a ridge structure obtained by chemical etching on a substrate made of semiconductor material, the ridge having a base and a top face, the guide having an outline with at least one curved section, the tangent at any point on the outline defining the local orientation (&bgr;) of the guide. According to the invention, the width of the base (weff) of the ridge is substantially constant all along the guide and the width of the top face (w) of the ridge varies according to the local orientation (&bgr;) of the guide with respect to the reference crystallographic direction (R) of the substrate.

Abstract: A method for growth of strain free epitaxial layers of semiconductors on highly lattice mismatched substrates is suggested using a buffer layer with a solid-liquid phase transition to accommodate high mismatch between substrate and semiconductor.

Abstract: A novel method of using rapid variation of temperature for generating driving energy to activating P-type compound semiconductor films and reducing the resistivity thereof. The P-type compound semiconductor films are made from III-V nitrides or II-VI group compounds doped with P-type impurity. In addition, the time duration when the ambient temperature is greater than a certain temperature during the annealing process is limited to be less than one minute. Therefore, the optoelectronic performance of the P-type compound semiconductor films will not degrade because the duration of annealing process is decreased.

Abstract: A semiconductor waveguide device and method for forming the same provide an InAlAs film as an etch stop layer. The InAlAs film does not etch in the CH4/H2 etch chemistry used to produce the device using reactive ion etching techniques. The etching process etches the waveguide layer and cladding layer or layers formed above the InAlAs layer, and exposes the InAlAs etch stop film to produce a waveguide device having desired physical characteristics.

Abstract: A method for manufacturing a ferroelectric memory cell includes the steps of forming a bottom electrode layer on a substrate, forming a ferroelectric thin film layer on the bottom electrode layer, forming a top electrode on the ferroelectric thin film layer, forming an encapsulating layer on the top electrode, forming a contact hole through the encapsulating layer, and co-annealing the ferroelectric thin film layer and the top electrode after forming the contact hole.

Abstract: The present invention relates to a method of manufacturing a silicon-on-insulator semiconductor wafer, including the steps of (1) forming a silicon-on-insulator semiconductor wafer having at least one surface of a monocrystalline silicon film; (2) contacting the at least one surface with phosphorus ions to form a doped region of the monocrystalline silicon film doped with phosphorus above a region of the monocrystalline silicon film which remains undoped; (3) subjecting the wafer to conditions to getter at least one impurity from the undoped region into the doped region; and (4) removing a portion of the monocrystalline silicon film including the doped region from the at least one surface, leaving a substantial portion of the monocrystalline silicon film.

Abstract: A self-aligned metal electrode sensor structure. The self-aligned metal electrode sensor structure includes a substrate which includes electronic circuitry. An interconnect structure is formed adjacent to the substrate. The interconnect structure includes conductive interconnect vias which pass through the interconnect structure. A sensor is formed adjacent to the interconnect structure. The sensor includes a pixel metallization section and a doped layer electrode. The pixel metallization section is electrically connected to the interconnect via. The pixel metallization section includes an outer surface which is substantially planar. The doped layer electrode includes an inner surface adjacent to the outer surface of the pixel metallization section. The entire inner surface of the doped layer electrode is substantially planar. A transparent conductive layer is formed adjacent to the sensor. The interconnect via and the transparent conductive layer electrically connect the electronic circuitry to the sensor.

Abstract: A method for fabricating a wafer level chip scale package with discrete package encapsulation and devices formed by the method are described. A dry film photoresist layer is first deposited on top of a pre-processed wafer complete with a plurality of bond pads and an I/O redistribution metal layer. The dry film photoresist layer is then patterned to form a plurality of trench openings and a plurality of via openings followed by the process of depositing a liquid photoresist material into the plurality of trench openings and plating a conductive metal into the plurality of via openings to form via plugs. After the dry film photoresist layer is removed, an encapsulant layer is printed on top of the wafer to embed the protrusions formed by the liquid photoresist material and the via plugs.

Abstract: A new, large-area, thin-film, flexible photovoltaic structure is disclosed, as well as a general fabrication procedure, including a preferably roll-to-roll-type, process-chamber-segregated, “continuous-motion”, method for producing such a structure. A special multi-material vapor-deposition environment is disclosed to implement an important co-evaporation, layer-deposition procedure performed in and as part of the fabrication procedure. A structural system adapted to create a vapor environment generally like that just referred to is disclosed, as is an organization of method steps involved in the generation of such a vapor environment. Also, a unique, vapor-creating, materials-distributing system, which includes specially designed heated crucibles with carefully arranged, spatially distributed, localized and generally point-like, heated-nozzle sources of different metallic vapors, and a special multi-fingered, comb-like, vapor-delivering manifold structure is shown.

Abstract: The invention relates to a II-VI semiconductor component in which, within a series of layers, there is provided at least one junction between a semiconductor layer containing BeTe and a semiconductor layer containing Se. A boundary layer between the semiconductor layer containing BeTe and the semiconductor layer containing Se is prepared in such a way that it forms a Be—Se configuration.

Abstract: In a two-dimensional image detector in accordance with the present invention, an active matrix substrate includes: a gate insulating film provided on gate electrodes and storage capacitance electrodes (Cs electrodes) provided in turn on a glass substrate; a first insulating protection layer and a second insulating protection layer sequentially provided on the gate insulating film; and pixel electrodes provided on the second insulating protection layer in a matrix. The second insulating protection layer is made of an acrylic resin, and its edges are completely covered with the photoconductor film.

Abstract: A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit.

Abstract: A method and apparatus for controlling the thickness of a semiconductor wafer during a backside grinding process are disclosed. The present invention uses optical measurement of the wafer thickness during a backside grinding process to determine the endpoint of the grinding process. Preferred methods entail measuring light transmitted through or reflected by a semiconductor wafer as a function of angle of incidence or of wavelength. This information is then used, through the use of curve fitting techniques or formulas, to determine the thickness of the semiconductor wafer. Furthermore, the present invention may be used to determine if wedging of the semiconductor occurs and, if wedging does occur, to provide leveling information to the thinning apparatus such that a grinding surface can be adjusted to reduce or eliminate wedging.

Abstract: The invention includes buried bit line memory circuitry, methods of forming buried bit line memory circuitry, and semiconductor processing methods of forming conductive lines. In but one implementation, a semiconductor processing method of forming a conductive line includes forming a silicon comprising region over a substrate. A TiNx comprising layer is deposited over the silicon comprising region, where “x” is greater than 0 and less than 1. The TiNx comprising layer is annealed in a nitrogen containing atmosphere effective to transform at least an outermost portion of the TiNx layer over the silicon comprising region to TiN. After the annealing, an elemental tungsten comprising layer is deposited on the TiN and at least the elemental tungsten comprising layer, the TiN, and any remaining TiNx layer is patterned into conductive line. In one implementation, a method such as the above is utilized in the fabrication of buried bit line memory circuitry.

Abstract: Polymer of parylene is desirable for an inter-level insulating layer because of a small dielectric constant; however, dimer/monomer of parylene is taken into a polymer layer during the deposition, residual dimer/monomer produces outgas during deposition of silicon oxide over the polymer layer, and the silicon oxide layer tends to peel off from the polymer layer; in order to prevent the resultant semiconductor structure layer from peeling of the silicon oxide layer, the polymer layer is annealed before the deposition of the silicon oxide for previously releasing the residual dimer/monomer from the polymer layer.

Abstract: This invention manufactures a photovoltaic device by the following process steps: a step to form a first electrode layer and a light-active semiconductor layer on an insulating surface of the substrate; a step to form a transparent conducting film over most of the insulating surface including the light-active semiconductor layer; a step to establish a patterned transparent protective layer on the transparent conducting film over power generating regions; and a step to irradiate ultraviolet laser light over most of the substrate to remove exposed portions of the transparent conducting film not masked by the pattered transparent protective layer and form a transparent conducting layer corresponding to the pattered transparent protective layer. The patterned transparent protective layer serves a dual purpose as masking material for removing the specified areas of the transparent conducting film by ultraviolet laser and as a transparent protective layer.

Abstract: The invention relates to a memory cell configuration in which a plurality of memory cells are present in the region of a main area of a semiconductor substrate (10), and in which the memory cells each contain at least one MOS transistor having a source (29), gate (WL1 and WL2) and drain (60). The memory cells are configured in memory cell rows which run essentially parallel, in which adjacent memory cell rows are insulated by an isolation trench (20), in which adjacent memory cell rows each contain at least one bit line (60), and where the bit lines (60) of two adjacent memory cell rows face one another. The memory cell configuration is constructed in such a way that the isolation trench (20) penetrates more deeply into the semiconductor substrate (10) than the bit lines (60), and at least one of the source (29) and/or of the drain is at least partially situated underneath the isolation trench (20). The invention furthermore relates to a method for fabricating this memory cell configuration.

Abstract: A technique based on etching a release layer, for separating the nearly lattice matched substrate from a base substrate is disclosed. A nearly lattice matched substrate for the epitaxial growth of Group-III nitride semiconductor devices and method of fabricating the nearly lattice matched substrate and devices is disclosed. Enhanced ELOG methods are used to create low defect density GaN films. The GaN films are used to grow Group-III nitride LEDs and laser diodes.

Abstract: The invention provides a method for depositing a film on a surface of a semiconductor wafer while preventing formation of defects on the surface of the wafer. The method includes selecting a quartz wafer carrier for holding the semiconductor wafer during the depositing of the film, where the wafer carrier has quartz rods with fire-polished slots for receiving an edge of the semiconductor wafer. The semiconductor wafer is placed into the quartz wafer carrier with the edge of the wafer disposed within the fire-polished slots, and the wafer carrier and wafer are loaded into a deposition chamber. Air is evacuated from the deposition chamber, the temperature in the chamber is raised to a deposition temperature, the pressure within the deposition chamber is adjusted to a deposition pressure, and process gases are introduced to the deposition chamber. By reaction of the process gases, the film is deposited on the surface of the wafer and on the wafer carrier.