Abstract: Processing of data in a higher language database management system is speed enhanced by the use of an external utility or subprogram which determines the amount of free memory available in working memory and selects a plurality of consecutive records from mass memory files which are then transferred as a file unit into a virtual record storage buffer in the working memory leaving just sufficient free working memory to accomplish required processing. The data in the records in the virtual record storage buffer is then continuously processed in the normal manner but without any time consuming intermediate selection of records. In improved versions of the method, the records are read initially into a primary buffer and process records are output through a secondary buffer which is desirably the same as the primary buffer. The utility is written in assembly language for additional speed.

Abstract: A method of handling a fault associated with a first floating point instruction upon reaching the next sequential floating point instruction is described. The first floating point instruction is decoded. A first floating point microinstruction received from a control memory is stored in a first latching means and in a second latching means. The next sequential floating point instruction is decoded. There is a jump to a plurality of exception handler microinstructions stored in the control memory, the jump occurring upon the detection of the fault associated with first floating point instruction. The plurality of exception handler microinstructions includes an exception handler floating point microinstruction. The exception handler floating point microinstruction received from the control memory is stored in the first latching means, replacing the previous microinstruction stored in the first latching means.

Abstract: A program is first analyzed in an ideal environment that assumes infinite processing resources and zero communication latency. In this environment, the program is viewed as being comprised of a plurality of steps of computation. Each step of computation is defined as the set of instructions that have all their operands available at that time. As such, each step of computation is limited only by data dependencies. The number of instructions executed for each step of computation is counted by the data processing system. The count of instructions may be used to produce an ideal parallelism profile that produces a graphical representation of the simulation. Having established an ideal level of parallelism in the ideal environment, a more realistic profile of the maximum level of parallelism may be obtained through analusis that accounts for a finite number of processors and for communication latency.

Abstract: A control system emulates a multi-tasking environment using a single tasking processor. A number of predefined tasks are provided in a task library. When a host application needs processed data from a data source, the host application creates a pipeline of initialized instantiations of one or more of the tasks from the task library. When the host application invokes the pipeline, the data request is made from the host application to a downstream-most section of the pipeline. The data request ripples upstreamwardly to the upstream-most instantiation of one of the tasks from the task library. The upstream-most instantiation of a task obtains data from a data source and returns it downstreamwardly to the host application, each instantiation of a task from the task library further operating on the data.

Abstract: An instruction fetch unit (640) of a data processor (610) capable of simultaneous execution of two instructions fetches a first and a second instruction from a memory (620) in one cycle. The first and the second instruction thus fetched are set in a first and a second register (641, 642) before being decoded in a first and a second instruction decoder (644, 645). Comparators (131, 132) compares data on the destination field of the first instruction with data on the source field of the second instruction. When both the data are inconsistent, a parallel operation control unit (646) permits the first and the second instruction execution unit (651, 652) under the first and the second instruction to execute the two instructions in response to the outputs of the comparators (131, 132). When both the data are consistent, the parallel operation control unit (646) inhibits the parallel execution.

Abstract: A method for the allocation of RAM memory space in a microcomputer environment allows for one or more terminate and stay resident (TSR) or other programs to be stored on a remote memory device in a way that preserves their accessability. The method includes the installation of a supervisory program which traps calls for a displaced program and transfers a portion of another program, such as an application-type program, in RAM to remote memory while retrieving the called displaced program from remote memory into the RAM space previously occupied by the transferred portion. The swap function is performed in a manner which preserves the integrity of the swapped program, and which allows operation of the application program to be halted such that it may be restarted without loss upon return from remote memory. In another aspect of the invention a communication TSR is simulated to allow data transfers to the TSR to be processed even if the TSR is in remote memory.

Abstract: A microcomputer constructed on a single semiconductor substrate comprises a microprocessor CPU, a read only memory ROM, a random access memory RAM, a common bus BUS for electrically connecting the microprocessor CPU, the read only memory ROM and the random access memory RAM, a plurality of timers TM, a plurality of input/output circuits I/O, a network portion NET for bringing the timers TM and the input/output circuits I/O into a desired connectional form, and a control register CRG for controlling the network portion NET.The control register CRG is coupled to the common bus BUS, and can have control bit information written thereinto by the microprocessor CPU. On the basis of the control bit information stored in the control register CRG, the network portion NET connects the timers TM and/or the input/output circuits I/O so as to achieve a specified circuit arrangement instructed by the control bit information.

Abstract: A method and apparatus for making a single CD-ROM disc useable on computers having unrelated operating systems or for multi-media platforms, specifically, wherein the two different operating systems are Hierarchical File System (HFS) used by Macintosh computers and MS-DOS which is the operating system used by IBM and compatible personal computers. The resulting compact disc is in ISO 9660 format which is a standard of the International Standards Organization which describes a logical format for organizing data on a Compact Disc Read Only Memory (CD-ROM). In this manner, it is possible to, for example, store two versions of a program on the same CD-ROM, one for execution on Macintosh computers and the other for execution on IBM PC and compatible computers. Thus, data which is to be stored on an ISO 9660 formatted disc can be sent from the producer or supplier of the data to a compact disc presser on a single magnetic medium such as a Bernoulli removable cartridge disk under a single operating system partition.

Abstract: A data processing system (10) implements a combined static and a dynamic masking operation of a breakpoint address. A static mask implements a conditional mask of a predetermined number of bits specified by the user and is determined prior to a comparison operation between the breakpoint address stored in a breakpoint register (24) and a logical address transferred via a logical address bus (11). A dynamic mask value implements a variable mask which allows the data processing system to mask the breakpoint address according to the size of a breakpoint address access. The static mask value and the dynamic mask value are combined using the same circuitry to form a combined mask value (19). Breakpoint function and address translation are implemented in the system (10) by using the same drive and control circuitry (20, 44, 48) to accomplish both functions. The breakpoint register (24) is implemented as an entry in a CAM array (26).

Abstract: A computer system in which each of certain critical instructions, all performing multiple main storage accesses to shared data, have the appearance of executing required main storage accesses atomically with respect to a predefined set or class of instructions.The instructions in each set, referred to as relatively atomic instructions, are grouped together based on the data structure or object class they affect.

Abstract: A processor capable of processing data of a structure having a first information field and a second information field includes conservation means for conserving the information of the predetermined second information field of the input data. Thus, in executing a logical operation or a shift operation, the step of separating the first data fields and second data fields from the data to-be-processed and the step of affixing the predetermined second field to the result of the operation are dispensed with, thereby to achieve a high-speed operation for the data of the structure having the first information field and the second information field.

Abstract: A device and method for generating execution controlling information (operation designating parameter) for an instruction execution means is provided. The device operates by selecting and composing a parameter (bit field) selected from among the bits of an instruction code and a parameter obtained as a result of decoding the instruction to be executed. The process makes it possible to reduce the size of a micro ROM by processing one instruction having various formats by the same micro-instruction.

Abstract: A microcontroller with the capability of allowing a user to expand the capabilities of the controller such that the added functionality performs as if the controller were designed with that added functionality onboard. This capability is implemented by providing at the pinouts of the controller access to a special function register area onboard the controller, as well as certain internal control signals. Each peripheral controller which is desired to be interfaced with the microcontroller must have a special address decoding block added. By use of the present invention, a microcontroller can be customized to a user's specifications without the costs associated with a custom designed chip.

Abstract: An improved system for checking for segmentation violations counts the total number of bytes accessed from the control segment following a control transfer operation. If the count indicates that a part of an instruction is fetched from outside the control segment a limit exception occurs.

Abstract: In a reconfigurable communications system, circuit status bits are stored in a first matrix of rows associated respectively with predefined network configurations and columns associated, respectively, with predefined circuit configurations. Destination status codes are stored in a second matrix of rows associated respectively with the circuit configurations and columns associated, respectively, with switching nodes of the system. Each circuit configuration comprises one or more transmission links, and each circuit status bit stored in each column of the first matrix pattern indicates the presence or absence of the circuit configuration associated with that column. Each destination status code indicates the presence or absence of transmission links from each switching node to possible destination nodes.

Abstract: A method and apparatus for instruction prefixing selectively reconfigures certain of the instructions in the microprocessor's instruction set so as to alter the nature of the operation performed by the instruction and/or the designation of operand or result locations accessed by the operation. A prefix instruction is inserted ahead of a "using" instruction and an operational parameter of the using instruction is modified in accordance with the contents of the prefix instruction. In one application, the prefix instruction may be used to specify a register location for storage of a result of the using instruction's operation or retrieval of an operand. In other applications, the prefix instruction may be used to modify other aspects of instruction execution.

Abstract: An instruction processor system for decoding compound instructions created from a series of base instructions of a scalar machine, the processor generating a series of compound instructions with an instruction format text having appended control bits in the instruction format text enabling the execution of the compound instruction format text in said instruction processor with a compounding facility which fetches and decodes compound instructions which can be executed as compounded and single instructions by the arithmetic and logic units of the instruction processor while preserving intact the scalar execution of the base instructions of a scalar machine which were originally in storage.

Abstract: Three high performance implementations for an interlock collapsing ALU are presented as alternative embodiments. The critical path delay of each embodiment provides reduction in delay. For one of the implementations the delay is shown to be an equivalent number of stages as required by a three-to-one adder assuming a commonly available bookset. The delay for the other two implementations is comparable to the three-to-one adder. In addition, trade-offs for the design complexity of implementation alternatives are set out. The embodiments achieve minimum delays without a prohibitive increase in hardware.

Abstract: A method and apparatus for implementing a sampling performance analysis for a selected application within a multi-thread operating system having a high degree of isolation between applications within the operating system. A trace function, such as the well known DosPtrace application program interface is established and utilized to control the execution of the selected application. The trace function is then utilized to insert a running thread program into the selected application which continuously generates breakpoint interrupts on a periodic basis. Each time a breakpoint interrupt is generated by the running thread program execution of the selected application is suspended and the current state of the selected application, including its location counter, is examined and stored. These stored indications of the state of the selected application are then utilized to automatically generate a report including a distribution of the execution times for the selected application.

Abstract: Arbitrary and complex Boolean functions can be evaluated at high speed and with a minimal amount of memory by evaluating the total derivatives of the subfunctions out of which any given Boolean function is built. The Boolean function is then generated from its total derivative. The total derivative of any binary or two input Boolean function is defined by a method dependent only on the inputs and the partial derivatives of the subfunction. By combining the subfunctions in a binary tree, a Boolean function of any complexity can be built up. By using a binary tree structure in a processing circuit or memory organization, the method is generalized to accommodate all possible Boolean functions.