Abstract: The bandwidth of a first bus and a second bus, unequal due to differences in protocol overheads and cycle times between the buses, are equalized without sacrificing any bandwidth on the lower bandwidth bus and without introducing any buffering in a control logic device. The control logic device equalizes the bandwidths of the buses by instructing a device coupled to the second bus to insert a partial dead bus cycle in a read transmission thereby dynamically adjusting read timing on the second bus when the second bus is heavily loaded.

Abstract: Input FIFO buffers serve to store sorted data. A number of the input FIFO buffers equals a first predetermined number N equal to 2.sup.n where n denotes a second predetermined number. A number of comparators equals the second predetermined number n. Intermediate FIFO buffers each have a capacity corresponding to at least two words. A number of the intermediate FIFO buffers equals the first predetermined number N minus 2. Identification numbers (i,j) are assigned to the intermediate FIFO buffers respectively wherein i=1, n-1 and where j=1, 2.sup.(n-1). A first of the comparators outputs a merge result of an i-th of the input FIFO buffers and an (i+N/2)-th of the input FIFO buffers to a (1,i)-th of the intermediate FIFO buffers where i=1, N/2. A j-th of the comparators outputs a merge result of a (j-1,i)-th of the intermediate FIFO buffers and a (j-1,i+2.sup.(n-i) -th of the intermediate FIFO buffers to a (j,i)-th of the intermediate FIFO buffers where j=2, n-1 and where i=1, 2.sup.(n-i).

Abstract: First and second instructions are simultaneously fetched from a memory to be respectively decoded by first and second instruction decoders. An instruction execution unit includes a register file, an arithmetic and logic unit, and a shifter. A first comparator compares a destination field of the first instruction with a first source field of the second instruction. The shifter produces an output in association with immediate data of the first instruction, the output being ordinarily stored in a register file. However, when both inputs of the comparator are identical to each other, the output from the shifter is supplied to an input of the arithmetic and logic unit via a bypass signal transmission path.

Abstract: A classification processing unit is disclosed for use with a computer having a register for storing classification data items and for storing data items respectively associated with the classification data items. The classification processing unit includes a comparator for receiving the classification data items from the register, which has an array of comparator units, each unit having a reference value for comparison with the classification data items. The processing unit also includes a classification pipline having an array of classification units respectively associated with the comparator units. The classification pipeline receives data items respectively associated with the classification data items and stores the data items respectively associated with said classification data items into the register in response to trigger signal from the comparator.

Abstract: A processing pipeline is disclosed for use with a computer having a vector register. The processing pipeline processes a logical expression including binary operand elements and operator elements successively supplied from the vector register, and stores resulting data into the vector register. The processing pipeline includes a first pushdown stack, coupled to the vector register to receive binary operand elements of the logical expression; a second pushdown stack, coupled to said vector register to receive operator elements of the logical expression; a character register to temporarily store an operator element of the logical expression during processing; and a processor for processing the logical expression, including an error detector for detecting errors in the logical expression based on a relationship between a first operator element in the character register and a second operator element at a top of the second pushdown stack.

Abstract: A portion of a real page address for address conversion and a remaining portion thereof are stored in predetermined areas of first and second memories for storing a control program and control data for controlling a channel apparatus. In order to control the channel apparatus, the first and second memories are independently accessed. In order to generate a DMA address, the first and second memories are simultaneously accessed, and data read out from the first and second memories are linked together to generate a real page address of an DMA-access objective area.

Abstract: A DMA controller has an attached, dedicated memory. Data objects are stored on the heap and connected by pointers. Each data object contains DMA block transfer control parameters. A single block transfer made up of several separate transfers, with each separate transfer defined by one data object. The single block transfer is defined by linking several data objects into a list. The DMA controller consecutively performs the transfers in a linked list without requiring control by a system central processor.

Abstract: Apparatus is described for evaluating an expression comprised of a plurality of subexpressions, each including at least one argument of a corresponding input value. The evaluating apparatus comprises a plurality of resolution modules disposed in an ordered sequence. Each resolution module corresponds to one of the input values and is adapted to perform at least one given function on its input value. Each of a plurality of logical groups of the resolution modules includes at least one resolution module and is related to a corresponding one of the subexpressions.

Abstract: An apparatus and method for controlling clusters having processors constituting a multiprocessor system. The apparatus includes a global control unit for processing orders between clusters and a memory control unit, provided in each cluster, for controlling transmission and reception of orders between the global control unit and the processors. Commands from one processor to another processor are sent to the memory control unit of the cluster containing the other processor and not directly to the other processor.

Abstract: Each of the identical register sets associated with each of the multiple channels of a peripheral device includes an initialization register. Setting the appropriate bit in the initialization register of any one of the channels allows the data processing system serviced by the peripheral device to perform a concurrent write operation to the same selected register in each channel enabled for a concurrent write. The concurrent write operation is based on a standard write instruction and a standard system address.

Abstract: A text processing method to be practiced by a handicapped person. A programmed computer has a dictionary of words stored in files accessed by selection of the initial letters of the words. The handicapped person operates one or more switches to designate the initial letter of the word. Thereafter, the switches are operated to control rapid searching of the designated file and selection of the desired word therefrom. The switches are also used for editing of text.

Abstract: A device and method for generating execution controlling information (operation designating parameter) for an instruction execution means is provided. The device operates by selecting and composing a parameter (bit field) selected from among the bits of an instruction code and a parameter obtained as a result of decoding the instruction to be executed. The process makes it possible to reduce the size of a micro ROM by processing one instruction having various formats by the same micro-instruction.

Abstract: Memory and peripheral chip select apparatus for allowing the addressing of different memory and peripheral elements by a processor. The different memory and peripheral elements include first memory elements and first peripheral elements located in a first adapter pluggable into a base machine and second memory elements and second peripheral elements located into a second adapter pluggable into the base machine. The processor further addresses third memory elements and third peripheral elements located in the base machine. The first and second memory elements include code which has a determined type and a determined level of release.

Abstract: A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit.

Abstract: A DOS computer system which effectively extends the DOS main memory capacity without the addition of supplemental random access memory (RAM) to the DOS main memory. The system enables application programs to be transferred from secondary hard disk memory to RAM on an as needed basis and enable active application programs in RAM to be placed in suspension in virtual memory for instantaneous recall to RAM to become active application programs and be executed from the point at which the application program was suspended for transfer to virtual memory.

Abstract: Methods and apparatus are described for processing branch instructions using a history based branch prediction mechanism (such as a branch history table) in combination with a data dependent branch table (DDBT), where the branch instructions can vary in both outcome and test operand location. The novel methods and apparatus are sensitive to branch mispredictions and to operand addresses used by the DDBT, to identify irrelevant DDBT entries. Irrelevant DDBT entries are identified within the prediction mechanism using state bits which, when set, indicate that: (1) a given entry in the prediction mechanism was updated by the DDBT and (2) subsequent to such update a misprediction occurred making further DDBT updates irrelevant. Once a DDBT entry is determined to be irrelevant, it is prevented from updating the prediction mechanism. The invention also provides methods and apparatus for locating and removing irrelevant entries from the DDBT.

Abstract: A self-sorting memory system (SSM) in which records to be sorted are stored in selected memory cells in random access memories. The system is constructed so that the amount of time required to sort the records depends only on the number of records to be sorted, that is, the sorting time depends upon the time required to feed the unsorted records serially into the system and the time required to output the sorted records serially from the system. The system also has the feature that additional unsorted records may be fed into the system and sorted with records already in the system after sorted records have been partially withdrawn from the system. The system is also capable of operating in a non-destruct mode in which sorted output records are returned to the system. For economical construction the system is made up of a plurality of identical modules, and the words making up each record are distributed among the modules for simultaneous processing.

Abstract: A data processing apparatus for decoding and executing instructions in a parallel manner in a variable word length instruction format. A plurality of decoders is used in which while the primary instruction decoder is decoding an instruction, the probability of parallel decoding of the next instruction is detected, so that the primary instruction decoder and a secondary instruction decoder decode a variable word length instruction and a fixed word length instruction, respectively, in a parallel manner. A conditional branch instruction of a fixed word length and the subsequent instruction of a variable word length are decoded and executed in a parallel manner to increase the speed at which the conditional branch instruction is executed.

Abstract: A cell architecture for use in a linear array wafer scale integration includes a plurality of multiplexers, each associated with a boundary of the cell, and each selectively operable to permit ingress to and egress from function logic of the cell by neighboring cells Each multiplexer is configured to receive and select between input and output busses from and to a neighbor cell adjacent the associated boundary. The output of each multiplexer connects to the output bus of the boundary adjacent to that with which the multiplexer is associated. When such cell architecture is used in wafer scale integration, oriented so that opposing sides of each cell are rotated 180 degrees relative to any cell at any boundary, the multiplexers can be configured to form a linear array of cells that ensures a fixed, known delay from function logic to function logic of the cells.

Abstract: A microprogram branching method and apparatus generate a continue address by successively incrementing an address, generate a branch address by referring to a branch address table depending on predetermined branch conditions, where the branch address table prestores branch addresses, discriminate whether or not a branch is to be made depending on the predetermined branch conditions and obtaining a discrimination result, select the continue address normally and selecting the branch address when the discrimination result indicates that the branch is to be made, and output a data which is read out from an address of a main memory depending on the selected address, where the main memory prestores microprograms.