Abstract: According to one embodiment, a semiconductor device includes a first circuit, a first terminal, a second terminal, a conductor and a first switch element serially coupled between the first terminal and the second terminal, wherein the first circuit is configured to turn the first switch element to an OFF state when a first condition is satisfied, and the conductor is configured to physically break when a second condition is satisfied.

Abstract: A level shifter with high reliability is shown, which has a cross-coupled pair and a pull-down pair. The cross-coupled pair couples a first power terminal to a first output terminal of the level shifter or a second output terminal of the level shifter. The pull-down pair has a first transistor and a second transistor, which are controlled according to an input signal of the level shifter. The first transistor is coupled between the second output terminal and a second power terminal, and the second transistor is coupled between the first output terminal and the second power terminal. A first voltage level coupled to the first power terminal is greater than a second voltage level coupled to the second power terminal, and the second voltage level is greater than the ground level.

Abstract: An network addressable lighting device that receives the input power from a power source (PSE), such as a network Power Over Ethernet (PoE) source, at a physical interface and data assembly PIDA and passes the signal directly to a second power assembly (PA) while the AC coupled high-speed data lines stay exclusively on the PIDA that contains the input and output physical interfaces, such as RJ interfaces. All power rails required to run the PIDA are converted on the PA and can then be sent back to the PIDA via low-cost conventional board stacker connectors. Movement of the high-current is done on the power assembly and not the data assembly where the sensitive communications primarily occur. The implementations thus provide an ideal separation of power and data structures to reduce EMI/EMC issues in a low cost and compact device.

Abstract: Techniques regarding a threshold scheme for quantum recommendation algorithms are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a quantum recommendation component that can project a preference vector onto a portion of a Hilbert space based on a value of a qubit phase register. The portion of the Hilbert space can encode singular values of a preference matrix that are greater than or equal to a defined threshold.

Abstract: A transmission gate includes a first P-type transistor and a second P-type transistor coupled in series between a first signal node and an internal node. The transmission gate is enabled by turning on the first P-type transistor and the second P-type transistor to communicate signals between the first signal node and the internal node. The transmission gate is disabled by turning off the first P-type transistor and the second P-type transistor to stop communicating signals between the first signal node and the internal node. While the transmission gate is disabled, a third P-type transistor having a first current electrode coupled to a circuit node between the first and second P-type transistors and a control electrode coupled to the first signal node is used to track voltage of the first signal node and, in response to the tracking, control a voltage level at the circuit node to limit a gate-to-source voltage of the first P-type transistor.

Abstract: An example circuit includes a plurality of light emitters connected in parallel between a first node and a second node. The circuit also includes a plurality of capacitors, with each capacitor corresponding to one of the light emitters, and a plurality of discharge-control switches, with each discharge-control switches corresponding to one of the capacitors. The circuit further includes a pulse-control switch connected to the plurality of light emitters. During a first period, the pulse-control switch restricts current flow, and each of the plurality of capacitors is charged via the first node. During a second period, one or more of the plurality of discharge-control switches allows current flow that discharges one or more corresponding capacitors. During a third period, the pulse-control switch allows current flow that discharges one or more undischarged capacitors of the plurality of capacitors through one or more corresponding light emitters.

Abstract: The present invention provides a driving device and a control method. The driving device is configured to drive a power switch and includes a power supply, a first bridge arm coupled to the power supply, a second bridge arm coupled in parallel to the first bridge arm, and a resonant inductor. The first bridge arm includes a first switch and a second switch connected to a first midpoint, the second bridge arm comprises a first semiconductor element and a second semiconductor element connected to a second midpoint, and the resonant inductor is coupled between the first midpoint and the second midpoint. The control method includes turning on the first switch for a first period such that the power supply charges a gate electrode of the power switch; and in response to a decrease of a current of the resonant inductor to a first threshold value, turning on the first switch again for a second period such that a potential of the first midpoint is equal to a potential of the second midpoint.

Abstract: Even when a large current is intentionally flowed during a high-temperature conduction of a semiconductor element, there is a problem in that an overcurrent state is detected to stop current. In the present invention, an overcurrent detector 4 detects overcurrent when an input voltage Vin reaches a threshold voltage Vth, and outputs an overcurrent detection signal c to a gate driving unit 3. On the other hand, when a temperature detection signal a and a current control signal b are input, a transistor 52 is conducted, and the input voltage Vin of the overcurrent detector 4 becomes zero. In this case, the input voltage Vin of the overcurrent detector 4 does not reach the threshold voltage Vth. Therefore, the output of the drive signal output from the gate driving unit 3 is not stopped. For this reason, a large current can flow in a drain current Ids.

Abstract: A power delivery system includes a controller, configured to receive a voltage indication signal indicating a measured voltage of a battery management system and to determine whether first and second diodes of the battery management system are faulty based on the voltage indication signal. The controller is also configured to respectively receive first and second current indication signals from first and second current sensors of the battery management system and to determine whether the first and second diodes of the first battery management system are faulty based on the first and second current indication signals.

Abstract: An analog switch circuit includes: a switch unit and a control circuit, wherein the control circuit includes a sensor circuit and a gate-source voltage adjustment circuit. The switch unit operates a first switch therein according to a first gate-source voltage, to convert an input signal of an input terminal to an output signal of an output terminal. The sensor circuit is coupled between the input terminal and the output terminal, and generates a sensing signal according to a voltage difference between the input signal and the output signal. The gate-source voltage adjustment circuit is coupled to the sensor circuit, and adaptively adjusts the first gate-source voltage according to the sensing signal, to maintain the conduction resistance of the switch unit at a constant while the voltage difference changes.

Abstract: The detection circuit includes a current source and a resistor element which are connected in series via a first node between a positive electrode and a negative electrode of a switching element which is turned on and off by a driving circuit. The voltage comparator outputs a detection signal indicating a comparison result between an input DC voltage and the voltage of the first node. The DC voltage and the electric resistance value of the resistor element are set in such manner that when an inter-electrode voltage between the positive electrode and the negative electrode becomes higher than a predefined determination voltage, the voltage of the first node is higher than the DC voltage. The detection circuit and the voltage comparator are mounted on the same integrated circuit constituting the semiconductor device.

Abstract: A circuit may include or may be coupled to a precharge structure to reduce or minimize a net perturbation, caused by switching, in the input source. Apparatus and techniques shown herein may enable low input current operation in a signal chain of an analog circuit by such reduction or minimization of such perturbation.

Abstract: A power module includes: a GaN transistor, an NMOS transistor, a first capacitor, a first diode and a second diode. The NMOS transistor is electrically connected to the GaN transistor. A negative electrode of the first capacitor is electrically connected to an anode of the first diode and a gate of the GaN transistor. A cathode of the second diode is electrically connected to a gate of the NMOS transistor. The power module further includes a power module control terminal electrically connected to an anode of the first capacitor and an anode of the second diode.

Abstract: A level-shifting output buffer has cascode transistors with varying rather than fixed gate bias voltages. An adaptive regulator bypasses the I/O pad voltage to a regulator output when the I/O begins switching, but later clamps the regulator output to a middle bias voltage. The regulator output can be applied to a supply terminal of a buffer that drives the gate of the cascode transistor. Since the adaptive regulator follows the I/O pad voltage as switching begins, a voltage boost is provided to the gates of the cascode transistors, allowing for higher currents or smaller cascode transistors and preventing over-voltage stress. The adaptive regulator has an n-channel bypass transistor between the I/O pad and the regulator output, and an n-channel clamp transistor between the regulator output and the middle bias, with a gate driven from the I/O pad by either a p-channel gate-biasing transistor or an n-channel gate-biasing transistor.

Abstract: In a first series circuit of a power supply control device, a first switch and a first resistor are connected in series. In a second series circuit, a second switch and a second resistor are connected in series. The second series circuit is connected in parallel to the first series circuit. An electric current detection circuit detects an electric current value of an electric current flowing through the first resistor. In a case where specific data is stored in a storage unit, a control unit (open failure detection unit) detects an open failure of the first switch or the second switch on the basis of the electric current value detected by the electric current detection circuit. In a case where the storage unit does not store the specific data, the control unit does not detect the open failure.

Abstract: A gate driver circuit includes first through third transistors, a first voltage clamp, and control logic. The first transistor has a first control input and first and second current terminals. The first current terminal couples to a first voltage terminal. The first voltage clamp couples between the first voltage terminal and the first control input. The second transistor couples between the first control input and the second voltage terminal. The third transistor couples between the first control input and the second voltage terminal. The third transistor is smaller than the second transistor. The control logic is configured to turn on both the second and third transistors to thereby turn on the first transistor, and the first control logic configured to turn off the second transistor after the first transistor turns on while maintaining in an on-state the third transistor to maintain the first transistor in the on-state.

Abstract: One embodiment provides a non-contact power transmitter device including a sealed housing provided at least partially within a surface, and a transmitter coil within the sealed housing configured to inductively transfer power to a power receiver device. The power transmitter device also includes a transmitter control unit coupled to the transmitter coil, a transceiver configured to communicate with the power receiver device, and an electronic processor coupled to the transmitter control unit and the transceiver. The electronic processor is configured to establish, using the transceiver, communication with the power receiver device, and negotiate power transfer requirements between the power transmitter device and the power receiver device. The electronic processor is also configured to control the transmitter control unit to transfer power to the power receiver device.

Abstract: Provided is an inductor stack structure. The inductor stack structure include a substrate; at least two metal layers sequentially stacked on one side of the substrate, each metal layer at least comprises a first plane inductor; a through hole, which is located between any two neighboring metal layers, first plane inductors in different metal layers are electrically connected through the through hole; and a thickness of the through hole is greater than that of the metal layer.

Abstract: Some embodiments provide a voltage-level shifter circuit comprising a cross-coupled transistor pull-up network that includes a plurality of diode-connected transistors configured to cause the state of the cross-coupled transistor network to switch at a low current through a pull-down network coupled thereto, such as a current corresponding to near-threshold voltage or sub-threshold voltage operation of the pull-down network.

Abstract: A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches.