Abstract: An apparatus, including a first circuit which contains a first load which does not draw current from a first battery when not operating, and includes an electric motor of an electric vehicle or hybrid vehicle; a second circuit which contains a second load which draws current from a second battery when the first load is not operating or is non-operational; a first switch which is capable of disconnecting the first battery from the first circuit; a second switch which is capable of connecting the first battery to the first circuit; and at least one recharger which is capable of recharging the first battery and the second battery when the first load is operating. The apparatus is capable of providing electrical power to the second load when the at least one recharger ceases to operate or becomes non-operational. The first load is an eaxle.

Abstract: A semiconductor integrated circuit includes a first oscillator configured to generate a first signal with a first frequency based on a control signal and output the first signal to a path. The semiconductor integrated circuit includes a control signal generation circuit operatively coupled to the first oscillator via the path, and configured to receive the first signal from the first oscillator via the path and generate the control signal. The semiconductor integrated circuit includes a second oscillator configured to generate a second signal with a second frequency based on the control signal and output the second signal to an output terminal outside the path.

Abstract: An apparatus includes a comparator. The comparator includes a plurality of pregain stages, and a switch network coupled to the plurality of pregain stages. The comparator further includes a latch coupled to the plurality of pregain stages.

Abstract: A voltage power switch includes circuitry configured to output a known voltage. The voltage power switch includes a lock circuit configured to output a known state and a voltage level shifter configured to receive an input, the input being based on the known state output by the lock circuit. The voltage power switch, using an output circuit, is configured to output a known voltage level based on an output of the voltage level shifter, wherein the known voltage is one of a high voltage VHI for a fuse programing period or a first non-zero intermediate voltage VMID1 for a non-fuse programming period.

Abstract: To provide a filter circuit and a semiconductor device capable of preventing circuit malfunction even when power supply voltage fluctuates. A filter circuit includes: a latch circuit configured to latch a set signal input to a first input terminal and a reset signal input to a second input terminal, respectively; and a rise adjustment unit configured to make a rise time of the set signal or the reset signal at power-on shorter than a time specified by a time constant circuit arranged in a preceding stage of the latch circuit.

Abstract: A switch system includes a bidirectional switch, a first gate driver circuit, a second gate driver circuit, a control unit, a first decision unit, and a second decision unit. The bidirectional switch includes a first source, a second source, a first gate, and a second gate. The first decision unit determines, based on a voltage at the first gate and a first threshold voltage, a state of the first gate in a first period in which a signal to turn OFF the first gate is output from the control unit to the first gate driver circuit. The second decision unit determines, based on a voltage at the second gate and a second threshold voltage, a state of the second gate in a second period in which a signal to turn OFF the second gate is output from the control unit to the second gate driver circuit.

Abstract: A switch control circuit and a switch control method are provided. The switch control circuit includes a load, an inductor, a control switch, and a sensing resistance connected in series to an input power source; an integrator that integrates a sensing voltage and a load current setting voltage to generate an integrated signal; a comparator that compares the integrated signal and a bias voltage; a switch driver that controls the control switch based on an output of the comparator and an output of an off time controller; and a gate sensor that outputs, to the integrator, a gate sensing signal that senses a time when an input of a gate terminal of the control switch becomes a low level. An integration operation is started from a position in which the integrated signal is located lower than the bias voltage, when an input of the gate terminal becomes a high level.

Abstract: Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.

Abstract: An improved gate driver using a microcontroller (uC), a voltage selector (VS), an adjustable voltage regulator (AVR), and an auxiliary current sinking circuit (ACSC) to actively provide selectable drive signals either higher, lower or equal to the basic on voltage and off voltage drive signals for a selected semiconductor device thereby providing an active voltage-mode gate driver for actively speeding up or slowing both the on time and off time transitions of a semiconductor.

Abstract: A switching apparatus includes three or more series-connected transistors, and it further includes a balancing network. The balancing network includes a resistor network configured to divide a voltage from a voltage source across the series-connected transistors. The resistor network includes at least two resistive legs connected in parallel. In each resistive leg, two or more resistors are connected in series. The balancing network may further comprise at least one capacitive leg of series-connected capacitors connected across the series-connected transistors, and it may further comprise at least one leg of series-connected avalanche diodes connected across the series-connected transistors for overvoltage protection. In example embodiments, the series-connected transistors are JFETs. In other example embodiments, the series-connected transistors may be HEMTs or GaN transistors.

Abstract: A radio frequency (RF) switch includes a switchable RF path including a plurality of transistors coupled in series; a gate bias network including a plurality of resistors, wherein the gate bias network is coupled to each of the plurality of transistors in the switchable RF path; and a bypass network including a first plurality of transistors coupled in parallel to each of the plurality of transistors in the switchable RF path and a second plurality of transistors coupled in parallel to each of the plurality of resistors in the gate bias network.

Abstract: According to one embodiment, a multichannel switch integrated circuit (IC) includes a multichannel switch circuit and a common test terminal. The multichannel switch circuit includes a plurality of switch circuitries. Each of the switch circuitries includes: an output transistor that outputs an output signal through an output terminal; an overcurrent detection circuit that detects a detection current according to a current flowing through the output transistor; and a diode having an anode that receives the detection current. The common test terminal is connected to each channel switch circuitry, connected to the overcurrent detection circuit through the diode, and connected to a cathode of the diode.

Abstract: A semiconductor apparatus includes a data input and output (input/output) circuit configured to operate by receiving a first voltage, a core circuit configured operate by receiving a second voltage, and a control circuit configured to output a power control signal for activating the data input/output circuit when the first voltage is higher than a first set voltage and the second voltage is higher a second set voltage.

Abstract: The present disclosure provides a controller for controlling a GaN-based semiconductor device. The controller is configured to receive a current sensing signal VCS which is indicative of a drain-to-source current of the GaN-based semiconductor device and generate a control driving signal VDRV to the GaN-based semiconductor device such that a gate-to-source voltage VGS applied to the GaN-based semiconductor device for switching on the GaN-based semiconductor device is stabilized to a voltage value equal to a reference voltage Vref over an on-time duration. Impact of the change in the voltage drop across the current sensing resistor to the operation of the GaN-based semiconductor device is eliminated.

Abstract: A solar powered smartphone case includes an enclosure for housing a smartphone, an internal battery, an overlying solar panel, an underlying solar panel, and a flip-out solar panel. The overlying solar panel and the flip out solar panel are carried back-to-back by a flip-out door, which articulates between a folded position and an extended position. A hinge pivotably attaches the flip-out door to the enclosure. An inductive battery charger is operative for charging the internal battery with electric power generated by the overlying solar panel, the underlying solar panel, and the flip-out solar panel. The case may also include an input port for receiving a first auxiliary power cord connecting one or more auxiliary solar panels to the inductive charger, and an output port for connecting a second auxiliary power cord connecting one or more piggy-back smartphones to be charged by the internal battery of the solar powered smartphone case.

Abstract: A N-path filter includes a plurality of switch-capacitor circuits controlled by a plurality of logical signals, respectively, and joined at a common shunt node, each of said switch-capacitor circuit comprising: a respective switch configured to controllably connect the common shunt node to a respective middle node in accordance with a respective logical signals among said plurality of logical signals; and a respective balanced MOS (metal oxide semiconductor) capacitor connected to the respective middle node, wherein the respective balanced MOS capacitor exhibits a capacitance at the respective middle node with reference to a power supply node and a ground node.

Abstract: A semiconductor device includes a hysteresis block configured to generate an output voltage at corresponding disabling enabling voltage levels and a core-voltage-gated (CVG) device configured to receive a core voltage, an input terminal of the hysteresis block is coupled to a control node. The CVG device is configured to alter a control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated at the disabling voltage level in response to the core voltage being at or below a first trigger level. Additionally, the CVG device is configured to alter the control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated at the enabling voltage level in response to the core voltage being at or above a second trigger level, the second trigger level being above the first trigger level.

Abstract: A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

Abstract: A method of generating multiple gating signals for a multi-gated input/output (I/O) system. The system includes an output level shifter and an output driver which are coupled in series between an output node of a core circuit and an external terminal of a corresponding system. The method includes: generating first and second gating signals having corresponding first and second waveforms, the first waveform transitioning from a non-enabling state to an enabling state before the second waveform transitions from the non-enabling state to the enabling state; receiving the first gating signal at the output level shifter; and receiving the second gating signal at the output driver.

Abstract: To provide a mobile phone which can be used without hampering convenience in a condition where functions of the mobile phone are switched and can improve operability. The mobile phone includes an optical sensor, a display element, a pixel circuit portion where a plurality of pixels having a plurality of transistors are arranged in matrix, an optical sensor control circuit which is connected to an optical sensor driver circuit for driving the optical sensor and reads a signal from the optical sensor, a display portion control circuit which is connected to a display element driver circuit for driving the display element and outputs an image signal for displaying an image on a display portion, a gradient detection portion for outputting a signal in accordance with a gradient of the mobile phone, and an arithmetic circuit for performing display in the pixel circuit portion by switching image signals output to the display portion control circuit with a signal from the gradient detection portion.