Patents Examined by Kenneth J. Ramsey
  • Patent number: 6458005
    Abstract: A selectively compliant chuck for assembling tiles into larger LCD displays facilitates alignment between a cover plate and a tile. A linear clutch is positioned between the tile chuck and the tile chuck carrier. This allows each chuck to float in the axis perpendicular to the tile's mating surface. The chuck has freedom to move linearly in this axis, and allows for pitch and roll motion as well. This floating connection can be turned on or off at will. Thus, a tile attached to the chuck can be lowered to intimately contact a cover plate and the chuck will compliantly move for high mating tolerances. Thereafter, the clutch can be locked to fix the chuck in it's current position. In this manner, the tile can be raised so that an adhesive can be applied to the cover plate. The tile can then be lowered back over the adhesive with the clutch locked and alignment maintained.
    Type: Grant
    Filed: July 19, 1999
    Date of Patent: October 1, 2002
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Baker, Ronald J. Becker, Allan O. Johnson, Ramesh R. Kodnani
  • Patent number: 6459198
    Abstract: A method of fabricating a high vacuum display with flat form factor, and the display, include an envelope with two major, parallel spaced apart glass sides and a continuous edge therebetween. An opening is formed through one of the glass sides of the envelope. A plate is provided with an area larger than the opening in the envelope. A button with an area slightly smaller than the opening may be formed on one side of the plate. A low temperature melting material is positioned on the plate around the button and the envelope is positioned in a substantial vacuum. The button is placed in the opening with the plate abutting the glass side outside of the envelope and the low temperature melting material is melted using heat and/or pressure to sealingly engage the button within the opening.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: October 1, 2002
    Assignee: Motorola, Inc.
    Inventors: Kenneth A. Dean, Babu R. Chalamala, Dave Uebelhoer, Craig Amrine
  • Patent number: 6456007
    Abstract: The present invention relates to a barrier structure for a PDP and a fabrication method thereof which are capable of enhancing a discharge efficiency by increasing a discharge space. The barrier structure according to the present invention includes a first barrier layer formed of an insulation substrate having a groove and plane portion formed thereon, and a rib-shaped second barrier layer formed on the plane area of the first barrier layer with respect to the groove. In the present invention, it is possible to increase the plasma discharge efficiency by increasing the coated area of the fluorescent material in the plasma discharge space and it is easy to fabricate the barriers having uniform heights for thereby enhancing a reliability of the PDP. In addition, it is possible to prevent an increase of the discharge voltage by adapting the barrier structure according to the present invention to the opposite electrode type PDP for thereby enhancing an efficiency of the PDP.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: September 24, 2002
    Assignee: LG Electronics Inc.
    Inventors: Byung-Gil Ryu, Jae-Sang Chung, Eun-Ho Yoo, Seok-Kon See
  • Patent number: 6450849
    Abstract: A fabricating method of a gas discharge display device having a dielectric layer spreading over an entire display area so as to cover electrodes arranged on a substrate, comprising arranging the electrodes on the substrate; and forming conformally the dielectric layer upon a surface of the substrate, on which the electrodes have been arranged, by the use of a plasma vapor deposition method. The fabricating method may further comprise forming a light shielding layer between the electrodes excluding at least the surface discharge gap within the display area before forming the dielectric layer.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: September 17, 2002
    Assignee: Fujitsu Limited
    Inventor: Hideki Harada
  • Patent number: 6450850
    Abstract: In a display panel manufacturing method and a display device manufactured by the method, a plate-shaped partition wall-forming member is sandwiched between a mold having an inverted shape to partition walls and a support mold to press-mold the partition wall-forming member therebetween, thereby forming a partition wall member comprising partition wall portions and a bottom insulating layer portion while coming into close contact with the mold. Thereafter, the partition wall member is transferred onto a display substrate to complete a display panel.
    Type: Grant
    Filed: January 19, 2000
    Date of Patent: September 17, 2002
    Assignee: NEC Corporation
    Inventor: Keiji Nunomura
  • Patent number: 6447355
    Abstract: There is provided an impregnated-type cathode substrate comprising a large particle diameter low porosity region and a small particle diameter high porosity region which is provided in a side of an electron emission surface of the large particle diameter low porosity region and has an average particle diameter smaller than an average particle diameter of the large particle diameter low pore region and a porosity higher than a porosity of the large particle diameter low porosity region, the impregnated-type cathode being impregnated with an electron emission substance.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: September 10, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiichirou Uda, Toshiharu Higuchi, Osamu Nakamura, Kiyomi Koyama, Sadao Matsumoto, Yoshiaki Ouchi, Kazuo Kobayashi, Takashi Sudo, Katsuhisa Homma
  • Patent number: 6447354
    Abstract: A process for fabricating high-aspect ratio support structures comprising: creating a rectangular fiber bundle by stacking selectively etchable glass strands having rectangular cross-sections; slicing the fiber bundle into rectangular tiles; adhering the tiles to an electrode plate of an evacuated display; and selectively removing glass strands, thereby creating support structures.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: September 10, 2002
    Assignee: Micron Technology, Inc.
    Inventors: James J. Hofmann, Jason B. Elledge
  • Patent number: 6445006
    Abstract: A microelectronic or microelectromechanical device, including a substrate and a carbon microfiber formed thereon, which may be employed as an electrical connector for the device or as a selectively translational component of a microelectromechanical (MEMS) device.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: September 3, 2002
    Assignee: Advanced Technology Materials, Inc.
    Inventors: George R. Brandes, Xueping Xu
  • Patent number: 6443788
    Abstract: A method for fabricating row lines and pixel openings of a field emission array that employs only two masks. A first mask is disposed over electrically conductive material and semiconductive material and includes apertures that are alignable between rows of pixels of the field emission array. Row lines of the field emission array are defined through the first mask. A passivation layer is then disposed over at least selected portions of the field emission array. A second mask, including apertures alignable over the pixel regions of the field emission array, is disposed over the passivation layer. The second mask is used in defining openings through the passivation layer and over the pixel regions of the field emission array. Conductive material exposed through the apertures of the second mask may also be removed to expose the underlying semiconductive grid and to further define the pixel openings.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: September 3, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Ammar Derraa
  • Patent number: 6443789
    Abstract: A device (10) for introducing hydrogen into a flat display (14) of the field emission or plasma addressed liquid crystal type is described, formed of a reservoir (11) containing a hydrogen accumulator material (21) connected to the internal space (13) of the display by means of a wall (15) permeable to the passage of hydrogen gas as a function of the temperature. The device comprises a heater (19) and a heater (22) for bringing respectively the wall and the accumulator material to the desired temperatures, or a single heater which carries out both cited functions. There is also described a method by which the device is activated whenever the flat display is working, the switching on of said heater being arranged in order to bring the wall itself to a previously calculated temperature.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: September 3, 2002
    Assignee: Saes Getters S.p.A.
    Inventors: Stefano Tominetti, Alessio Corazza
  • Patent number: 6439943
    Abstract: The object of the present invention is to provide a high-intensity, reliable plasma display panel even when the cell structure is fine by resolving the problems such as a low visible light transmittance and low voltage endurance of a dielectric glass layer. The object is realized by forming the dielectric glass layer in the manner given below. A glass paste including a glass powder is applied on the front glass substrate or the back glass substrate, according to a screen printing method, a die coating method, a spray coating method, a spin coating method, or a blade coating method, on each of which electrodes have been formed, and the glass powder in the applied glass paste is fired. The average particle diameter of the glass powder is 0.1 to 1.5 &mgr;m and the maximum particle diameter is equal to or smaller than three times the average particle diameter.
    Type: Grant
    Filed: May 11, 1999
    Date of Patent: August 27, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaki Aoki, Yasuhisa Ishikura, Katsuyoshi Yamashita, Shinya Fujiwara, Yasuyuki Akata
  • Patent number: 6435928
    Abstract: An electron-emitting device comprises a pair of electrodes and an electroconductive thin film therebetween having an electron-emitting region. The electroconductive thin film is coated with an additional film at the electron-emitting region to provide an additional resistance within a range from 500&OHgr; to 100 k&OHgr;.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: August 20, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takeo Tsukamoto
  • Patent number: 6428378
    Abstract: A field emission display having a base plate which has a focus ring structure substantially planar with the extraction grid. The field emission display base plate is fabricated on a substrate having a cathode including an emitter tip formed thereon by depositing a first insulating layer, a first conductive layer over the first insulating layer, etching the first conductive layer, depositing a second insulating layer over the etched first conductive layer, and depositing a second conductive or focus ring layer over the second insulating layer. A second selective etching may be formed to further define the gate and focus ring structures.
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: August 6, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Kevin W. Tjaden, Terry N. Williams
  • Patent number: 6428377
    Abstract: A colored DC plasma display panel having a plurality of sub-pixels organized in a matrix configuration. The color DC plasma display panel includes a first plate having a first substrate. A plurality of rows of cathodes are formed on the first substrate which include a plurality of holes therein spaced along each cathode row; preferably one hole for each sub-pixel. A dielectric layer covers the cathode rows and the substrate, and a plurality of holes are formed in the dielectric layer which align with the holes in the cathodes. The color DC plasma display panel further includes a second plate having a second substrate and a pluarility of rows of anodes formed on and extending along the length of the second substrate. The anodes reside in channels created between a pluarality of rows of barrier ribs formed on the second substrate.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: August 6, 2002
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung Cheol Choi
  • Patent number: 6428379
    Abstract: A high-pressure discharge lamp includes a glass housing made of a high-melting vitreous material, a pair of sealing components made of the same high-melting vitreous material and extended from the glass housing. A rare gas and a material that is solid or liquid at room temperature is sealed inside the glass housing. Electrically conductive bars are embedded in the sealing components. The air-tight seals around the electrically conductive bars are formed such that at least one metal material selected from metals and oxides of said metals is provided near the regions lying between the high-melting vitreous material and the electrically conductive bar.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: August 6, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuriko Kaneko, Makoto Horiuchi, Mamoru Takeda
  • Patent number: 6425791
    Abstract: A field emission device is disclosed having a buffer layer positioned between an underlying cathode conductive layer and an overlying resistor layer. The buffer layer consists of substantially undoped amorphous silicon. Any pinhole defects or discontinuities that extend through the resistor layer terminate at the buffer layer, thereby preventing the problems otherwise caused by pinhole defects. In particular, the buffer layer prevents breakdown of the resistor layer, thereby reducing the possibility of short circuiting. The buffer layer further reduces the risk of delamination of various layers or other irregularities arising from subsequent processing steps. Also disclosed are methods of making and using the field emission device having the buffer layer.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: July 30, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Kanwal K. Raina, James J. Alwan
  • Patent number: 6425793
    Abstract: An impregnated cathode and a method of manufacturing the same are provided for suppressing emission of unwanted electrons and particles generated from an excess electron emitting substance so as to achieve a steady electron emission characteristic. The impregnated cathode is placed directly beneath an electron emission hole of a first grid. The impregnated cathode is made up of a first sintered porous element whose surface functions as an electron emitting region and a second sintered porous element whose surface is a peripheral region other than the electron emitting region. The porosity of the first sintered porous element is greater than that of the second sintered porous element. Not only the first sintered porous element having the electron emitting region but also the second sintered porous element corresponding to the region around the electron emitting region is impregnated with the electron emitting substance.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: July 30, 2002
    Assignees: Sony Corporation, Citizen Watch Co., Ltd., Cimeo Precision Co., Ltd.
    Inventors: Yoji Hasegawa, Shinji Ogawa, Daichi Imabayashi, Makoto Furukawa, Nobuyuki Yoshino, Junji Sato, Yoshirou Hirai, Naoto Ogasawara, Kuniyasu Kobayashi
  • Patent number: 6426588
    Abstract: An airtight vessel is formed with restraining a vacuum leak and without increase in the number of steps. Provided is a method for producing an image-forming apparatus comprising the airtight vessel in which a rear plate having an electron-emitting device and a wire connected to the element, and a face plate having an electrode are joined to each other through a jointing material, the method comprising the following steps: (A) a first step of forming a first wire which is a part of the wire and which passes through the joint part to connect the inside of the vessel to the outside, by applying a paste comprising particles of an electric conductor and baking the paste; and (B) a second step of forming a second wire located in the vessel, by applying a paste comprising particles of an electric conductor so as to be connected to the first wire inside the vessel and baking the paste, after formation of the first wire.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: July 30, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoshihiro Yanagisawa
  • Patent number: 6425792
    Abstract: Disclosed is a method for producing an electrochromic device in which to provide an opening in the surface of each of the two electrically conductive substrates of the cell, not in the end surface of the opposed substrates, to insert into one of the openings an elastically deformable sealing member; to fill the inside of the cell by vacuum-injecting an electrolyte or the precursor thereof through the other opening which remains open; to push the sealing member up to the opening for injecting the electrolyte or the precursor so as to dose this opening as well; and to bond the sealing member extending through the two openings to each of the substrates with an adhesive.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: July 30, 2002
    Assignee: Nippon Mitsubishi Oil Corporation
    Inventors: Tomohiro Toya, Yukio Kobayashi, Yoshinori Nishikitani
  • Patent number: 6422906
    Abstract: A process is disclosed for anodically bonding an array of spacer columns to one of the inner major faces on one of the generally planar plates of an evacuated, flat-panel video display. The process includes the steps of: providing a generally planar plate having a plurality of spacer column attachment sites; providing electrical interconnection between all attachment sites; coating each attachment site with a patch of oxidizable material; providing an array of unattached permanent glass spacer columns, each unattached permanent spacer column being of uniform length and being positioned longitudinally perpendicular to a single plane, with the plane intersecting the midpoint of each unattached spacer column; positioning the array such that an end of one permanent spacer column is in contact with the oxidizable material patch at each attachment site; and anodically bonding the contacting end of each permanent spacer column to the oxidizable material layer.
    Type: Grant
    Filed: July 8, 1999
    Date of Patent: July 23, 2002
    Assignee: Micron Technology, Inc.
    Inventors: James J. Hofmann, Jason B. Elledge, Zhong-Yi Xia, David A. Cathey