Patents Examined by Kenneth J. Ramsey
  • Patent number: 6579139
    Abstract: Disclosed is a method, for forming a film locally on a substrate, which comprises the steps of detecting the state of the substrate employing the obtained result to calculate positional information concerning a plurality of locations at which the material for the film is to be provided to form the film, and providing the material for the film at the plurality of locations based on the positional information that is obtained for the plurality of locations.
    Type: Grant
    Filed: February 11, 1999
    Date of Patent: June 17, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Seiji Mishima, Mitsutoshi Hasegawa, Kazuhiro Sando, Kazuya Shigeoka
  • Patent number: 6579140
    Abstract: A method for fabricating row lines and pixel openings of a field emission array that employs only two masks. A first mask is disposed over electrically conductive material and semiconductive material and includes apertures that are alignable between rows of pixels of the field emission array. Row lines of the field emission array are defined through the first mask. A passivation layer is then disposed over at least selected portions of the field emission array. A second mask, including apertures alignable over the pixel regions of the field emission array, is disposed over the passivation layer. The second mask is used in defining openings through the passivation layer and over the pixel regions of the field emission array. Conductive material exposed through the apertures of the second mask may also be removed to expose the underlying semiconductive grid and to further define the pixel openings.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: June 17, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Ammar Derraa
  • Patent number: 6575801
    Abstract: Method for fabricating a cathode in a cathode ray tube, the cathode having a cathode sleeve with a heat radiative coating layer formed on an inside wall thereof for emission of thermal electrons, the heat radiative coating layer being formed by a method including the steps of (a) coating a material of the heat radiative coating layer on a surface of a metal wire provided separately, (b) inserting the metal wire having the heat radiative coating layer coated thereon, to pass through an opening the cylindrical cathode sleeve, and (c) heating the metal wire by providing a power thereto, to deposit the material of the heat radiative coating layer coated on the metal wire on the inside wall of the cathode sleeve, whereby permitting to coat many number of cathode sleeves at a time, and to form a film of uniform composition and even thickness to enhance electron emission.
    Type: Grant
    Filed: November 7, 2000
    Date of Patent: June 10, 2003
    Assignee: LG Electronics Inc.
    Inventors: Gyeong Sang Lee, Byoung Doo Ko, Young Deog Koh, Dawa Yashiro, Matsuo Tosihiro, Huruya Koushi, Yagima Taeruo
  • Patent number: 6572425
    Abstract: Electron emission structures formed using standard semiconductor processes on a substrate first prepared with a topographical feature are disclosed. At least one layer of a first material is concurrently deposited on the substrate and etched from the substrate to form an atomically sharp feature. An at least one layer of a second material is deposited over the atomically sharp feature. A conductive layer is deposited over the at least one layer of the second material. A selected area of material is removed from the conductive layer and the at least one layer of second material to expose the atomically sharp feature. Finally, electrical connectivity is provided to elements of the electron emission structure.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: June 3, 2003
    Assignee: Intel Corporation
    Inventors: Michael A. Maxim, Oleh Karpenko, Farshid Adibi-rizi, Brett E. Huff
  • Patent number: 6572426
    Abstract: An x-ray tube is provisionally assembled by interposing an upright part (12A) projecting from a first brazing agent (A) between a stem (3) and a bulb (2), and by interposing a second brazing agent (B) between the bulb (2) and an output window (4). This temporary assembly is conveyed into a vacuum brazing oven (P). Since a gap (K) is provided between the stem (3) and the bulb (2) by the upright part (12A), gas inside the bulb (2) can be discharged through the gap (K). Then, the vacuum brazing oven (P) is heated to a predetermined temperature to melt the first and second brazing agents (A, B), to thus fuse-bondingly fix the stem (3) and the output window (4) to the bulb (2). Brazing connection is completed in the vacuum brazing oven (P) while maintaining the sealed vessel (7) in a high vacuum condition without provision of a discharge pipe in the stem (3).
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: June 3, 2003
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Tutomu Inazuru
  • Patent number: 6568978
    Abstract: A method for producing an electrode substrate, having an organic insulating region formed of an organic insulating material and an inorganic insulating region formed of an inorganic insulating material on an identical side thereof, includes the steps of performing a plasma treatment of the organic insulating region; forming a first transparent conductive layer in contact with the organic insulating region and a second transparent conductive layer in contact with the inorganic insulating region; and etching the first transparent conductive layer and the second transparent conductive layer in the same step.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: May 27, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshiharu Kataoka, Takashi Fujikawa, Masafumi Kokura
  • Patent number: 6568979
    Abstract: A field emitter cell includes a thin-film-edge emitter normal to the gate layer. The field emitter cell may include a conductive substrate layer, an insulator layer having a perforation, a gate layer having a perforation, an emitter layer, and other optional layers. The perforation in the gate layer is larger and concentrically offset with respect to the perforation in the insulating layer and may be of a tapered construction. Alternatively, the perforation in the gate layer may be coincident with, or larger or smaller than, the perforation in the insulating layer, provided that the gate layer is shielded from the emitter from a direct line-of-sight by a nonconducting standoff layer. Optionally, the thin-film-edge emitter may include incorporated nanofilaments. The field emitter cell has low gate current, making it useful for various applications such as field emitter displays, high voltage power switching, microwave, RF amplification and other applications that require high emission currents.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: May 27, 2003
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: David S. Y. Hsu
  • Patent number: 6565402
    Abstract: A cathode structure comprises a cylindrical metal sleeve having aperture portions at both ends, a base metal having an aperture portion on one end, which is fitted onto one of the aperture portions of the metal sleeve, and an electron-emitting layer, which is formed on a flat portion of an outside surface of the base metal. After an electron-emitting material is sprayed onto the base metal, its surface is mechanically flattened to form the electron-emitting layer. Thus, the planarity of the surface of the electron-emitting layer can be improved without deterioration of the electron emission characteristics and the moiré can be decreased without reduction of the resolution.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: May 20, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahide Yamauchi, Satoru Nakagawa, Yoshikazu Iwai
  • Patent number: 6565403
    Abstract: Patterned ion-bombarded graphite electron emitters are disclosed as well as processes for producing them. The electron emitters are produced by forming a layer of composite of graphite particles and glass on a substrate then bombarding the composite with an ion beam. The electron emitters are useful in field emitter cathode assemblies which are fabricated into flat panel displays.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: May 20, 2003
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Daniel Irwin Amey, Jr., Robert Joseph Bouchard, Syed Ismat Ullah Shah
  • Patent number: 6565401
    Abstract: A getter film is formed on an inner surface of a funnel portion of a cathode ray tube, and an inner conductor of the cathode ray tube is heated by a heating unit. According to this heating, the gas which is physically adsorbed by the inner conductor of the cathode ray tube other than the getter film is discharged and then chemically adsorbed again by the getter film, whereby a degree of vacuum in the cathode ray tube can be increased.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: May 20, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takeshi Sugano, Etsushi Adachi, Chikayuki Nakamura, Wataru Imanishi
  • Patent number: 6565400
    Abstract: A method for attaching a faceplate and a backplate of a field emission display device. Specifically, one embodiment of the present invention discloses a method for protecting a silicon nitride passivation layer from reacting with a glass frit sealing material that contains lead oxide during an oven sealing or laser sealing process. The passivation layer protects row and column electrodes in the display device. A barrier material fully encapsulates the silicon nitride passivation layer. In one embodiment, silicon dioxide is the barrier material. In another embodiment, spin-on-glass is the barrier material. In still another embodiment, cermet is the barrier material.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: May 20, 2003
    Assignee: Candescent Technologies Corporation
    Inventors: Jueng-Gil Lee, Paul N. Ludwig, Melissa Skocypec
  • Patent number: 6561864
    Abstract: A process for fabricating high-aspect ratio support structures comprising: creating a rectangular fiber bundle by stacking selectively etchable glass strands having rectangular cross-sections; slicing the fiber bundle into rectangular tiles; adhering the tiles to an electrode plate of an evacuated display; and selectively removing glass strands, thereby creating support structures.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: May 13, 2003
    Assignee: Micron Technology, Inc.
    Inventors: James J. Hofmann, Jason B. Elledge
  • Patent number: 6558219
    Abstract: A method of forming an electroluminescent device, including the steps of forming a first charge carrier injecting layer for injecting charge carriers of a first polarity, forming an organic charge carrier transport layer over the first charge carrier injecting layer, the transport layer having an electronic and/or optical property which varies across the thickness of the transport layer, forming an organic light emissive layer over the transport layer, and forming a second charge carrier injecting layer over the light emissive layer for injecting charge carriers of a second polarity.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: May 6, 2003
    Assignee: Cambridge Display Technology Limited
    Inventors: Jeremy Henley Burroughes, Christopher John Bright, Karl Pichler, Peter Ho
  • Patent number: 6554672
    Abstract: An evacuated cavity is hermetically sealed between a baseplate and faceplate of a flat panel display. Melting a glass powder, or frit, on the perimeter of the viewing area forms the hermetic seal. After melting the frit, a first fluid is circulated through the cavity to speed cooling. To further expedite the cooling of the flat panel display, a second fluid flows externally along the contour of the flat panel display to insure that the cooling is uniform and thereby avoid thermal shock.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: April 29, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Craig M. Dunham, Seungwoo Lee, Jim Browning, Michel Garcia
  • Patent number: 6554671
    Abstract: A process is disclosed for anodically bonding an array of spacer columns to one of the inner major faces on one of the generally planar plates of an evacuated, flat-panel video display. The process includes the steps of: providing a generally planar plate having a plurality of spacer column attachment sites; providing electrical interconnection between all attachment sites; coating each attachment site with a patch of oxidizable material; providing an array of unattached permanent glass spacer columns, each unattached permanent spacer column being of uniform length and being positioned longitudinally perpendicular to a single plane, with the plane intersecting the midpoint of each unattached spacer column; positioning the array such that an end of one permanent spacer column is in contact with the oxidizable material patch at each attachment site; and anodically bonding the contacting end of each permanent spacer column to the oxidizable material layer.
    Type: Grant
    Filed: August 2, 2000
    Date of Patent: April 29, 2003
    Assignee: Micron Technology, Inc.
    Inventors: James J. Hofmann, Jason B. Elledge
  • Patent number: 6554673
    Abstract: A method for fabricating an electron emitter. This emitter structure may be used to form individual emitters or arrays of emitters. The method is comprised of implanting energetic ions into a diamond lattice to form cones or other continuous regions of damaged diamond. These regions are more electrically conducting than the surrounding diamond lattice, and have locally sharp tips at or near the point of entry of the ion into the diamond. The tips may then also be additionally coated with a layer of a wide band-gap semiconductor. An electrically conducting material may also be placed in proximity to the tips to generate an electric field sufficient to extract electrons from the conducting tips into either the region above the surface, or into the wide band-gap semiconductor layer in contact with the tips.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: April 29, 2003
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Pehr Pehrsson, James Butler
  • Patent number: 6554670
    Abstract: A holder having a funnel-shaped portion is provided above an eyelet, and a conductive metal piece is supplied to the vicinity of a portion at which plasma arc welding is performed in the funnel-shaped portion. The conductive metal piece is fused together by plasma arc welding so that the hole of the eyelet is closed completely. Thus, the lead wire can be connected firmly. Therefore, even if the hole diameter of the eyelet is excessively large relative to the diameter of the lead wire, complete closure and sufficient fusion connection can be achieved.
    Type: Grant
    Filed: May 18, 2000
    Date of Patent: April 29, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Gunji Eto
  • Patent number: 6552478
    Abstract: Each pixel of a field emission device includes a resistor with at least one emitter tip thereover and at least one substantially vertically oriented conductive element positioned adjacent the resistor. In a field emission array, a conductive element may contact each resistor of a line of pixels. A method for fabricating the field emission array includes forming a plurality of substantially parallel conductive lines, depositing at least one layer of semiconductive or conductive material over and laterally adjacent each conductive line, and forming a hard mask in recesses of the surface of the uppermost material layer. The underlying material layer or layers are patterned through the hard mask, exposing substantially longitudinal center portions of the conductive lines. The remaining semiconductive or conductive material is patterned to form the emitter tips and resistors. At least the substantially central longitudinal portions of the conductive traces are removed to form the conductive elements.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: April 22, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Ammar Derraa
  • Patent number: 6547617
    Abstract: The present invention intends to provide a manufacturing method for a PDP that can continuously apply phosphor ink for a long time and can accurately and evenly produce phosphor layers even when the cell construction is very fine. To do so, phosphor ink is continuously expelled from a nozzle while the nozzle moves relative to channels between partition walls formed on a plate so as to scan and apply phosphor ink to the channels. While doing so the path taken by the nozzle within each channel between a pair of partition walls is adjusted based on position information for the channel. When phosphor particles is successively applied to a plurality of channels, phosphor ink is continuously expelled from the nozzle even when the nozzle is positioned away from the channels. The phosphor ink is composed of: phosphor particles that have an average particle diameter of 0.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: April 15, 2003
    Inventors: Hiroyuki Kawamura, Shigeo Suzuki, Masaki Aoki, Kanako Miyashita, Mitsuhiro Ohtani, Hiroyuki Kado, Keisuke Sumida, Nobuyuki Kirihara
  • Patent number: 6547618
    Abstract: A method of fabricating a high vacuum device by providing two major, parallel spaced apart glass sides in a substantial vacuum, forming a continuous edge between the sides and forming a tack with a metallic diffusion bond between the sides. The metallic diffusion bond is formed of materials that bond and cure faster than the material of the continuous edge so that the tack holds the sides in a fixed position while the continuous edge is curing.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: April 15, 2003
    Assignee: Motorola, Inc.
    Inventors: Alan L. James, Kevin M. Reinhart