Abstract: Mapping of cacheable memory pages from other processes in a parallel job provides a very efficient mechanism for inter-process communication. A trivial address computation can then be used to look up a virtual address that allows the use of cacheable loads and stores to directly access or update the memory of other processes in the job for communication purposes. When an interconnection network permits the cacheable access of one host's memory from another host in the cluster, kernel and library software can map memory from processes on other hosts, in addition to the memory on the same host. This mapping can be done at the start of a parallel job using a system library interface. A function in an application programming interface provides a user-level, fast lookup of a virtual address that references data regions residing on all of the processes in a parallel job running across multiple hosts.

Abstract: Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in and a storage plug-in. The eviction policy plug-in includes code to evict an object that is cached in the region of cache. The storage plug-in includes code to execute a function involving an object manipulation function that gets a first object located within the region of cache, and an attribute manipulation function that gets a specific attribute for the first object from within the region of cache.

Abstract: Typical embodiments of the present invention maintain the cache metadata in arrays, and use vector instructions to process the array elements in parallel. The cache metadata comprises virtual tags corresponding to main memory addresses and physical addresses corresponding to cache memory addresses. The virtual tags and physical addresses may be interleaved in a single array in the cache memory. Alternately, virtual tags and physical addresses may be maintained in corresponding separate arrays. A roving pointer may be used to identify the next block to be ejected from the cache memory.

Abstract: Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.

Abstract: This invention is a system and method related to restoring data in a data storage environment and includes program logic.

Abstract: In a data storage system, events are associated with the state of a data set at specific points in time, the data set being a collection of addressable storage that is modified by a host computer system writing to specific addresses, by capturing copies of writes made by the host to the data set, each copied write having write data and address. Sequence information is assigned to the captured writes to organize the captured writes in the time sequence in which the writes were captured. Absolute time information is assigned to each captured write. Each captured write is retained as an entry in a repository, the entry including write data, address, sequence information, and absolute time information. An event is associated to a specific entry in the repository. The association is retained for subsequent use.

Abstract: A storage has NAS and SAN functions and a high degree of freedom to configure a system to reduce the management and operation cost. The storage includes a plurality of interface slots in which a plurality of interface controllers can be installed, a block I/O interface controller which has SAN functions and which can be installed in the slot, a file I/O interface controller which has NAS functions and which can be installed in the slots, a storage capacity pool including a plurality of disk devices accessible from the interface controllers, and a storage capacity pool controller to control the storage capacity pool.

Abstract: A method, apparatus and computer program product are provided for implementing feedback directed deferral on nonessential direct access storage device (DASD) operations. A kernel DASD I/O manager maintains a queue depth count value for a DASD unit and maintains a busy flag that indicates when the queue depth count value is greater than a predefined threshold. The kernel DASD I/O manager defers optional operations responsive to the busy flag being set for the DASD unit.

Abstract: Systems and methods of processing addresses provide for receiving a full linear address of an instruction and reducing a size of the full linear address to obtain a reduced linear address. A data block can be retrieved from a data array if the reduced linear address corresponds to a tag in a tag array, where the tag array is associated with the data array. The reduced linear address enables the tag array to either be smaller in size or achieve enhanced performance. The data array may be a prediction array of a branch predictor or a cache array of a cache.

Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive status information from circuit logic that collects the status information from caches associated with different processor cores. The software also causes the processor to provide the information to a user of the software. The status information indicates whether one of the caches comprises an entry associated with a virtual address.

Abstract: Methods and systems for preserving content of serial use devices in view of a purge are presented. A method for preserving content of a serial use device in view of a purge may comprise: detecting a likelihood that a purge of a memory of a serial-use device is forthcoming; and transmitting a content of the memory of the serial-use device in response to said detecting. A system for preserving content of a serial use device in view of a purge may comprise: means for detecting a likelihood that a purge of a memory of a serial-use device is forthcoming; and means for transmitting a content of the memory of the serial-use device in response to said detecting.

Abstract: Memory management within a runtime execution environment may be configured in accordance with data associated with executable code loaded therein.

Abstract: A method and system for efficiently migrating in-use small pages to enable promotion of contiguous small pages into large pages in a memory environment that includes small pages pinned to real memory and/or and small pages mapped to direct memory access (DMA) within real memory. The operating system is designed with a two-phase page promotion engine/utility that enables coalescing contiguous small virtual memory pages to create large virtual memory pages by migrating in-use small memory pages including those that are pinned and/or mapped to DMA.

Abstract: A method and system for virtual storage element placement within a storage area network is disclosed. According to one embodiment of the present invention, first data is received which specifies an access characteristic of a virtual storage element to be associated with a storage area network. Once received, the first data is used along with second data specifying a topology of a storage area network to select a virtualization device of the storage area network. According to another embodiment of the present invention, third data specifying a characteristic of one or more virtualization devices of the storage area network is additionally used to select the virtualization device. Thereafter, the virtual storage element to be associated with the storage area network is associated with the selected virtualization device.

Abstract: Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in. The eviction policy plug-in includes an eviction timing component and a sorting component, with the eviction timing component including code to implement an eviction timing method, and the eviction timing method to trigger eviction of an object from the region of cache. The sorting component includes code to implement a sorting method to identify an object that is eligible for eviction from said region of cache.

Abstract: Methods of managing memory devices, and devices so managed. A value of a parameter, that is used to program one or more memory cells, is adapted to a monitored condition of the cell(s). Either the number of bits per cell is held fixed or the monitored condition is an intrinsic condition of the cell(s). The initial value of the parameter is optimized for those specific cells, relative to a pre-selected criterion, by programming the cell(s) in accordance with candidate values of the parameter.

Abstract: For use in a storage area network (SAN), a virtualization layer including at least one virtual engine having a respective local cache and a secondary cache layer, wherein the secondary cache layer includes the local caches coupled together, the local caches individually including a first cache layer, and at least one of a data transfer command and data corresponding to the transfer command are multicast to the secondary cache layer through an interconnection bus, the interconnection bus coupling the at least one virtual engine and at least one physical storage device.

Abstract: A multithread control apparatus and control method to switch a plurality of threads in a multithread processor, which includes a plurality of thread processors to execute the plurality of threads, by executing a synchronization lock control by considering release of exclusive access right to a relevant thread processor when a particular block in caches is updated with another processor or another thread processor during execution of a certain thread processor.

Abstract: A computer-implemented method of realizing an associative memory capable of storing a set of documents and retrieving one or more stored documents similar to an inputted query document, said method comprising: coding each document or a part of it through a corresponding feature vector consisting of a series of bits which respectively code for the presence or absence of certain features in said document; arranging the feature vectors in a matrix; generating a query feature vector based on the query document and according to the rules used for generating the feature vectors corresponding to the stored document s such that the query vector corresponds in its length to the width of the matrix; storing the matrix column-wise; for those columns of the matrix where the query vector indicates the presence of a feature, bitwise performing one or more of preferably hardware supported logical operations between the columns of the matrix to obtain one or more additional result columns coding for a similarity measure betw

Abstract: Storage destination controller devices wherein N number of data strips and M number of parity strips comprised in each stripe are determined so that the parity strips are not continuously stored to the same memory device between two consecutive stripes when a plurality of stripes, each comprising the N number of data strips and the M number of parity strips of different types, are distributed and stored to the N+M number of memory devices.