Abstract: In a method of managing a cache directory in a memory system, an original system address is presented to the cache directory when corresponding associativity data is allocated to an associativity class in the cache directory. The original system address is normalized by removing address space corresponding to a memory hole, thereby generating a normalized address. The normalized address is stored in the cache directory. The normalized address is de-normalized, thereby generating a de-normalized address, when the associativity data is cast out of the cache directory to make room for new associativity data. The de-normalized address is sent to the memory system for coherency management.

Abstract: According to one embodiment of the invention, a processor comprises a memory, a plurality of processor cores in communication with the cache memory and a scalability agent unit that operates as an interface between an on-die interconnect and both multiple processor cores and memory.

Abstract: A method of ensuring that data sent to a handheld wireless communications device is written to non-volatile memory is disclosed. In a device, where data is initially written to a first volatile memory and then written to a second volatile memory before being written from the second volatile memory to a non-volatile memory, software code is implemented that causes the writing of the data to non-volatile memory concurrently with the writing of the data to the second volatile memory. The software code may incorporate operating system commands (such as Windows OS).

Abstract: A host computer system is configured to present each of multiple resident contexts with an address space that may be mapped, at least in part, to corresponding portions of a host memory. The address space of a selected context is sampled, and, for each of a plurality of sampled portions of the address space of the selected context that are backed by a corresponding portion of host memory, a count of the number of portions of address spaces of any contexts that are backed by the same portion of the host memory is obtained. A metric is then computed as a function of the count. A decision about swapping out or reclaiming the allocation of the memory of the contexts is based on the metric. The metric is preferably a function of a mean (such as harmonic, geometric or arithmetic) or median of the counts for each context.

Abstract: A memory control method includes writing converted data which is produced by carrying out a code conversion on original data into a memory. An amount of 1s in the converted data is less than an amount of 1s in the original data. Further, the memory control method includes outputting reproduced data which is provided by carrying out an inverse transformation of the code conversion on the converted data which is read out from the memory, to a host system for processing the original data.

Abstract: Various methods and systems for synchronizing replicas using a single change map are disclosed. One method involves detecting a write to a first region of a volume, while synchronization of the volume with a replica volume is ongoing. If the first region is unsynchronized with respect to a corresponding region of the replica volume, replication of the write is inhibited. Otherwise, the write is replicated. Writes for which replication is inhibited will be applied to the replica volume at a later time as part of the ongoing synchronization.

Abstract: A caching device is positioned between a memory read/write controller and a flash memory, which contains an instruction register, a logical address register, a data register, a pair of auxiliary controllers, a microprocessor, an address translation unit, a flash memory address register, a caching control unit, and a caching instruction and data buffer area. Among them, the microprocessor is the core of the caching device responsible not only for the reading and writing the flash memory but also for the caching operation for logical and physical address translation. The caching control unit is a programmable device containing the instruction and data for caching the logical and physical address mapping. The caching instruction and data buffer area temporarily stores the caching instruction and data used by the caching control unit.

Abstract: A system architecture for implementing a virtual disk service (VDS) equipment is applicable for implementing an overall management on multiple service request objects in a VDS system. The system architecture includes a VDS interface, a subsystem management module, an object management module, a virtual disk management module, and a specific management module. The VDS interface receives a service request, and renders the service request to the subsystem management module for judging a type of the service request. The virtual disk management module generates a plurality of virtual interfaces for being invoked by the subsystem management module, so as to execute the service request of a public operation type. When the service request requires for supporting an asynchronous processing, the specific management module is further invoked to process the service request, and generates a feedback result to respond the service request via the VDS interface.

Abstract: A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of the first feedback circuit, based on the logic level of a first clock signal. The second latch has a second feedback circuit and a second selecting circuit which selects an output signal of the first latch and an output signal of the second feedback circuit based on the inverted logic level in case of the first latch. The first feedback circuit has a third selecting circuit which selects one of an output signal of the first latch and a second data input signal based on the logic level of a second clock signal, and outputs a signal selected by the third selecting circuit to the first selecting circuit.

Abstract: A first read request is received from a computer system. Data from one mirror of a data volume is returned to the computer system in response to receiving the first read request. The computer system may check the returned data to determine whether it is corrupted. If corrupted, the computer system sends a second read request for the same data. Rather than returning the same corrupted data stored in the one mirror, a copy of the requested data is returned from an alternate mirror of the data volume.

Abstract: Provided is a method for removing alias addresses from an alias address pool. A plurality of alias addresses are assigned to an alias address pool, wherein the alias addresses in the alias address pool are capable of being dynamically assigned to a device to service I/O requests to the device. An operation is initiated by a process to remove a specified alias address from the alias address pool. An indicator is set to prevent additional processes from removing one alias address from the alias address pool in response to initiating the operation. The specified alias address is removed from the alias address pool.

Abstract: Provided are a method, system, and program for allocating call stack frame entries at different memory levels to functions in a program. Functions in a program accessing state information stored in call stack frame entries are processed. Call stack frame entries are allocated to the state information for each function, wherein the call stack frame entries span multiple memory levels, and wherein one function is capable of being allocated stack entries in multiple memory levels.

Abstract: A memory controller is described that comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information. A processor and a memory controller integrated on a same semiconductor die is also described. The memory controller comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information.

Abstract: A memory control unit includes fuses that are selectively blown to set a manufacturer's identification code (ID), and a further fuse that is selectively blown to designate the memory control unit as a general-purpose unit or a custom unit. When designated as a custom unit, the memory control unit uses the manufacturer's ID to protect data in the memory by scrambling the data, or by comparing the manufacturer's ID with an input ID and disabling access to the memory if the ID's do not match. A semiconductor integrated circuit chip including the memory control unit can thus be fuse-programmed for either general-purpose use or custom use.

Abstract: A data storage system is provided comprising several flash arrays in a board and stacking these boards to attain a high-capacity solid state hard drive. A remap table is used to map all logical addresses from a host system to the actual physical addresses where data are stored. The assignments of these physical locations are done in such a way that the load of the system is evenly distributed to its available resources. This would ensure that the storage system will run at its utmost efficiency utilizing its resources properly. To achieve this, the system would make sure that the physical location of data be evenly distributed according to the current load of the system.

Abstract: Disclosed is apparatus and methods for enabling an appliance to receive data being sent between any host of a host cluster to a specified storage device's logical unit (LUN) in a single stream or session. In one embodiment, a data virtual target is initially set up for a specified storage device LUN so that data written from a host to the specified storage device LUN is received by the DVT. An appliance then sends a session request to mirror data that is sent to the DVT (and specified storage device LUN) to a specified LUN of the appliance. The session request is not host specific. That is, data that is sent by any host to the DVT is mirrored to the same appliance LUN.

Abstract: In some embodiments, reformat logic comprises a plurality of registers and translation logic that accesses the registers. The translation logic receives a memory access targeting an application data structure that has a different format than accesses permitted to be provided to a device, which may be a display. The translation logic reformats the request to a format compatible with the device based on values stored in the registers.

Abstract: Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in and a storage plug-in. The eviction policy plug-in includes code to evict an object that is cached in the region of cache. The storage plug-in includes code to execute a function involving a key attribute manipulation function that, using a first hashing function and a key, identifies a table of attributes for the first object located within the region of cache, and using a second hashing function and an attribute name, gets a specific attribute for the first object from the table, the key being registered with the storage plug-in.

Abstract: Embodiments generally relate to a method of reducing latency and cost. A device access request is received in a memory of non-local node over a NUMA interconnect from a source node. The device access request is forwarded to an off-node controller from the memory of the non-local node. The device access request completion notification and data is forwarded to the source node.

Abstract: In a data processing system having a memory control device including at least two mirrored memory ports, a method and computer-readable medium for processing read requests are disclosed herein. In accordance with the method of the present invention, a read request is received on a system interconnect coupling read requestors with memory resources. The received read request is issued only to a specified one of the at least two mirrored memory ports within the memory control device. In response to detecting an unrecoverable error resulting from the read request issued to the one mirrored memory port, the received read request is issued to an alternate of the at least two mirrored memory ports.