Patents Examined by Kevin Ellis
  • Patent number: 8060703
    Abstract: Techniques for allocating/reducing storage required for one or more virtual machines are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for allocating storage for one or more virtual machines. The method may comprise providing one or more virtual machines. The method may also comprise creating one or more master images containing one or more commonly used blocks. The method may also comprise creating one or more Copy on Write volumes, where each Copy on Write volume may be associated with at least one of the one or more virtual machines and at least one of the one or more master images, and wherein updated blocks may be stored in at least one of the one or more Copy on Write volumes, thereby reducing storage required for one or more virtual machines.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: November 15, 2011
    Assignee: Symantec Corporation
    Inventors: Komal Desai, Jonathan Purcell, Bruce Montague, Viswesvaran Janakiraman, Douglas Fallstrom, Rajeev Bharadhwaj
  • Patent number: 8060684
    Abstract: Memory control apparatus, memory control method, and program are provided. The present invention provides a preparatory process for determining whether or not a data-updating process to update data of a flash memory or a data-writing process to write new data into the memory has been completed normally. A data-updating process to update data stored in a specific block is carried out as a process including alternate-block processing to replace the specific block with another block referred to as an alternate block. In the current data-updating process, the alternate block is examined to determine whether or not data has been erased from the alternate block. If data has been erased from the alternate block, the preceding data-updating or data-writing process is determined to be normal. By virtue of a property exhibited by the contents of the reserved-block address, the reserved-block address needs to be saved in the flash memory only once during a data-updating or data-writing process.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: November 15, 2011
    Assignee: Sony Corporation
    Inventors: Kenichi Nakanishi, Nobuhiro Kaneko
  • Patent number: 8055839
    Abstract: A storage manager application implemented in a first computational device maintains a virtual logical volume having a plurality of segments created by the storage manager application, wherein space is reserved at the end of a physical volume corresponding to the virtual logical volume, and wherein the physical volume comprises a linear storage medium. A request is received to write data, at the first computational device, from a second computational device. The data is written to the reserved space, wherein the writing of the data causes new segments to be created in the reserved space.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gregory Tad Kishi, Josephn M. Swingler
  • Patent number: 8055837
    Abstract: A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: November 8, 2011
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Kang Yeh, Chien-Hua Chu, Jia-Yi Fu
  • Patent number: 8051250
    Abstract: A system for pushing data, the system includes a source node that stores a coherent copy of a block of data. The system also includes a push engine configured to determine a next consumer of the block of data. The determination being made in the absence of the push engine detecting a request for the block of data from the next consumer. The push engine causes the source node to push the block of data to a memory associated with the next consumer to reduce latency of the next consumer accessing the block of data.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: November 1, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Blaine D Gaither, Darel N. Emmot, Judson E. Veazey, Benjamin D. Osecky
  • Patent number: 8051245
    Abstract: It is recognized that an attached USB memory is an unanalyzable USB memory. Then, disconnect setting is made. A USB connection process is performed. A PC is instructed through a connection line to establish USB connection. The PC recognizes that the attached device is a USB-connected MFP. The PC acquires data control information of the MFP. The MFP then transfers, through the connection line, the data control information output from the USB memory.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: November 1, 2011
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Minako Kobayashi, Takehisa Yamaguchi, Katsuhiko Akita, Kazuya Anezaki
  • Patent number: 8051254
    Abstract: A storage device including a logical volume being a migration source of an application copies data stored in the logical volume being a migration source into a logical volume being a migration destination of the application. After such a copy process is started, the storage device stores the data written into the logical volume being a migration source as differential data without storing the data into the logical volume being a migration source. When the copy process is completed for the data stored in the logical volume being a migration source, a management computer starts copying of the differential data, and in a time interval after the copying of the data stored in the logical volume being a migration source is completed but before the copying of the differential data is completed, a computer being a migration destination of the application is turned ON. With such a logically-partitioned computer system, power consumption at the time of application migration can be reduced.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: November 1, 2011
    Assignee: Hitachi, Ltd.
    Inventor: Tomohiko Suzuki
  • Patent number: 8051261
    Abstract: A method of locating a storage device of a number of storage devices is provided. A request for a data item is received. The request includes a globally unique identifier (GUID) that is associated with a user. A start number is generated based on the GUID, and the storage device that stores the data item is located based on the start number. The data item is then read from the located storage device. Other techniques for locating a storage device are also described.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: November 1, 2011
    Assignee: eBay Inc.
    Inventors: Jean-Michel Leon, Louis Marcel Gino Monier
  • Patent number: 8046521
    Abstract: A hypervisor prepares a guest region identifier (RID)-physical region identifier (RID) mapping table for dynamically registering and managing items and performs RID conversion using the guest RID-physical RID mapping table. When the mapping table is used, since it is unnecessary to provide a specific information area representing logical partitions (LPARs) corresponding to respective guests in an RID to be converted, there is no limitation concerning the number of LPARs and a problem in operation can be eliminated.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: October 25, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Souichi Takashige, Tomoki Sekiguchi, Tomohide Hasegawa
  • Patent number: 8041916
    Abstract: A data storage device and a method of operating the same include firmware recognizing that the data storage device has a smaller than normal capacity or includes a routine in the firmware when the number of bad blocks exceeds the maximum. Therefore, even if the number of bad blocks exceeds the maximum, the data storage device having a capacity smaller than the normal capacity can be used.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-jeong Nam
  • Patent number: 8041876
    Abstract: A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application within a host machine context and executing a virtual machine application within a virtual machine context. A plurality of TLB (translation look aside buffer) entries for the virtual machine context and the host machine context are stored within a TLB. Memory protection bits for the plurality of TLB entries are logically combined to enforce memory protection on the virtual machine application.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: October 18, 2011
    Inventor: H. Peter Anvin
  • Patent number: 8037250
    Abstract: In one embodiment, a processor comprises a cache and a cache miss unit coupled to the cache. The cache is coupled to be accessed by cache accesses corresponding to a plurality of threads active in the processor. The cache miss unit is configured to record a plurality of cache misses detected in the cache and to associate each cache miss of the plurality of cache misses with a corresponding thread of the plurality of threads for which that cache miss is detected. Additionally, the cache miss unit is configured to initiate a cache fill for a selected cache miss of the plurality of cache misses. The cache miss unit is configured to select the selected cache miss based on a prioritization of the corresponding threads associated with the plurality of cache misses. In one implementation, the cache is an instruction cache and the cache misses are due to fetches corresponding to the plurality of threads.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: October 11, 2011
    Assignee: Oracle America, Inc.
    Inventors: Jama I. Barreh, Manish K. Shah
  • Patent number: 8037231
    Abstract: Code, data, and/or other information types, may be isolated from one another and stored in distinct regions within the memory array of a nonvolatile memory. The distinct regions in memory may have corresponding read/write interfaces that are optimized for each information type.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: October 11, 2011
    Assignee: Intel Corporation
    Inventor: Sean Eilert
  • Patent number: 8032717
    Abstract: A data storage control apparatus and method for reduction of traffic of an interconnect occurring in the timing of a cache miss within a CPU. The apparatus and method are realized by utilizing, as a response to the read request from the CPU, data tags DTAGs used for management of data registered to the cache memory within the CPU under the control of a local node and a retention tag used for holding secondary data indicating that the object data is not held in the cache memory of any CPU of a local node.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: October 4, 2011
    Assignee: Fujitsu Limited
    Inventor: Shigekatsu Sagi
  • Patent number: 8032731
    Abstract: A virtualization system, upon judging that a write operation from a higher-level device is an operation to write in the format of the virtual volume, even when the write position of the write operation is in a virtual area different from a virtual area to which an allocated actual area has been allocated, if there is an unused area in the allocated actual area, writes management information to the unused area according to the write operation, and if there is no unused area in the allocated actual area, newly allocates an unallocated actual area, and writes management information to the newly allocated actual area according to the write operation.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: October 4, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Shintaro Inoue, Yutaka Takata, Mikio Fukuoka, Eiju Katsuragi, Hisaharu Takeuchi
  • Patent number: 8032728
    Abstract: A digital data reproducing apparatus comprising: a reading unit configured to read digital data stored in a recording medium at a speed higher than a reproduction speed to store the digital data into a first memory; an encoding unit configured to store encoded data obtained by encoding the digital data read by the reading unit into a second memory; a reproducing unit configured to reproduce the digital data stored in the first memory at the reproduction speed; and a transferring unit configured to transfer the encoded data stored in the second memory into a third memory different from the second memory.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: October 4, 2011
    Assignees: Sanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Akira Hashimoto, Masatoshi Sato
  • Patent number: 8032719
    Abstract: A method of managing a memory resource is provided for the storage of a plurality of sequentially received data elements, each data element comprising a plurality of data integers, the method comprising prior to storing a received data element, checking if the available storage capacity of the memory resource is less than a predetermined threshold value and in response to the available storage capacity being less than the predetermined threshold value, deleting at least one data integer from at least one of the data elements stored in the memory resource.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: October 4, 2011
    Assignee: Tektronix International Sales GmbH
    Inventor: Matthew A. Bowers
  • Patent number: 8032704
    Abstract: A method and apparatus for storing data on a computer data storage system are described. Two or more computers are coupled together to form a cluster of computers. One or more data storage devices are coupled to the two or more computers. One or more volumes of data storage devices are implemented on a plurality of computers of the two or more computers, where each volume is a logical arrangement of the one or more storage devices coupled to a selected computer of the plurality of computers. A data container holds data stored by the data storage system. The data container is striped over a plurality of the one or more volumes of data storage devices, whereby data stored in the data container is striped over a plurality of the volumes of data storage devices.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: October 4, 2011
    Assignee: NetApp, Inc.
    Inventors: Peter F. Corbett, Robert M. English, Steven R. Kleiman
  • Patent number: 8032732
    Abstract: A cache-aware Bloom filter system segments a bit vector of a cache-aware Bloom filter into fixed-size blocks. The system hashes an item to be inserted into the cache-aware Bloom filter to identify one of the fixed-size blocks as a selected block for receiving the item and hashes the item k times to generate k hashed values for encoding the item for insertion in the in the selected block. The system sets bits within the selected block with addresses corresponding to the k hashed values such that accessing the item in the cache-aware Bloom filter requires accessing only the selected block to check the k hashed values. The size of the fixed-size block corresponds to a cache-line size of an associated computer architecture on which the cache-aware Bloom filter is installed.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporatio
    Inventors: Kevin Scott Beyer, Sridhar Rajagopalan
  • Patent number: 8028145
    Abstract: A data storage device that performs a process of writing to a memory a plurality of measured data sets received in time series includes: a nonvolatile memory divided in a plurality of blocks to which the measured data is written; and a write control section that performs a processing including successively writing N sets of the measured data to a given block in the nonvolatile memory, and then successively writing next N sets of the measured data to another block, wherein the write control section judges whether or not the N sets of measured data lastly written to the given block of the nonvolatile memory and another N sets of measured data obtained after the N sets of measured data lastly written to the given block contain data with a value outside a predetermined range, writes new measured data to the given block such that the N sets of measured data lastly written to the given block are not overwritten when the data with a value outside the predetermined range is included, and writes new measured data to t
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: September 27, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Shinichi Fukada