Abstract: A computer system including a first storage system connected to a first host computer, a second storage system connected to a second host computer and a third storage system connected to the first and second storage systems. The second storage system sets transfer setting before an occurrence of a failure, the transfer setting being provided with a dedicated storage area to be used for transferring data to the third storage system by asynchronous copy in response to a failure at the first host computer. Before the start of data transfer between the second storage system and third storage system to be executed after an occurrence of the failure, the second storage system checks the dedicated storage area, data transfer line and transfer setting information, and if an abnormal state is detected, this abnormal state is reported to the host computer as information attached to the transfer setting.

Abstract: A swap space is provided for a host computer system, where the swap space includes a plurality of swap files with each individual swap file for swapping data only for a single corresponding virtual machine (VM). The per-VM swap space is used solely by the single, corresponding VM, such that only that particular VM's memory is allowed to be swapped out to the swap file.

Abstract: A method and computer program product for defining a multicast group within a local area network. The multicast group includes a storage initiator device, a plurality of storage targets, and one or more coded targets. A write request for storing a data segment within the multicast group is received on the storage initiator device. The data segment is multicast to the plurality of storage targets and the one or more coded targets included within the multicast group. A unique data chunk of the data segment is stored on each of the plurality of storage targets. A unique coded chunk of the data segment is generated and stored on each of the one or more coded targets.

Abstract: A system, method and computer program product for receiving on a non-volatile, solid-state, cache memory system, a data segment, including a plurality of data elements, from one or more of a volatile, solid-state, cache memory system and a non-volatile, electromechanical memory system. The data segment may be stored on the non-volatile, solid-state, cache memory system. Each data element includes one or more data extents.

Abstract: A method and computer program product for defining a multicast group within a local area network. The multicast group includes a storage initiator device and a plurality of storage targets. Each of the plurality of storage targets includes a storage index that identifies one or more data segments stored on the storage target. A write request for storing a data segment within the multicast group is received on the storage initiator device. A “check exist” message is generated that defines the data segment to be stored within the multicast group. The “check exist” message is multicast to the plurality of storage targets included within the multicast group.

Abstract: A method of wear leveling for a non-volatile memory is disclosed. A non-volatile memory is divided into windows and gaps, with each gap between two adjacent windows. The windows comprise physical blocks mapped to logical addresses, and the gaps comprise physical blocks not mapped to logical addresses. The windows are shifted through the non-volatile memory in which the mapping to the physical blocks in the window to be shifted is changed to the physical blocks in the gap.

Abstract: The memory access device includes: a plurality of command division sections provided for a plurality of masters; a plurality of inter-master arbitration sections provided for a plurality of banks; and a memory control section. Each of the command division sections divides a command issued by the corresponding master into a plurality of micro-commands when the access region of the command is over two or more banks among the plurality of banks, each of the micro-commands being a command accessing only one of the two or more banks, and gives each of the micro-commands to an inter-master arbitration section corresponding to the bank including the access region of the micro-command. Each of the inter-master arbitration sections arbitrates micro-commands given from the command division sections to select one. The memory control section selects one of a plurality of micro-commands selected by the inter-master arbitration sections to perform memory access.

Abstract: A log-based FTL and an operating method thereof for improving performances of reading and writing operations to increase the lifetime of a flash memory. In the method, when a reading operation for an LBN and an LPN is requested, a PBN and a PPN corresponding to the LBN and the LPN are calculated with reference to a pagemap corresponding to the LBN. A physical page of a physical block corresponding to the PBN and the PPN is accessed so that a reading operation is performed. On the other hand, when a writing operation for the LBN and the LPN is requested, a PBN and a PPN for a free-page of a physical block last assigned for the LBN are calculated with reference to a blockmap. The physical page of the physical block corresponding to the PBN and the PPN is accessed, so that a writing operation is performed. The pagemap stores a PBN and a PPN, and the blockmap stores a PBN list and a PPN.

Abstract: An embodiment of a method of forming a virtual computer cluster within a shared computing environment begins with a step of placing gatekeeper software on each of a plurality of particular host computers of the shared computing environment. The method continues with a step of assigning computing platforms located on the particular host computers to the virtual computer cluster. The gatekeeper software interposes between the computing platforms and hardware resources of the particular host computers. The method concludes with a step of isolating the virtual computer cluster from a remainder of the shared computing environment using the gatekeeper software. The gatekeeper software allows communication between the computing platforms while precluding communication with other computing platforms of the shared computing environment. The gatekeeper software controls input and output operations for the virtual computer cluster.

Abstract: A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. The virtualization platform including Virtual Machine Monitor (VMM) managed components coupled to the VMM. One of the VMM managed components is a TPM (Trusted Platform Module). The virtualization platform also includes a plurality of Virtual Machines (VMs). Each of the virtual machines includes a guest Operating System (OS), a TPM device driver (TDD), and at least one security application. The VMM creates an intra-partition in memory for each TDD such that other code and information at a same or higher privilege level in the VM cannot access the memory contents of the TDD. The VMM also maps access only from the TDD to a TPM register space specifically designated for the VM requesting access. Contents of the TPM requested by the TDD are stored in an exclusively VMM-managed protected page table that provides hardware-based memory isolation for the TDD.

Abstract: An architecture for an integrated circuit with in-circuit programming allows real-time modification of the in-circuit programming code and other code stored on the chip. The architecture utilizes a microprocessor and control logic on an integrated circuit having a single non-volatile memory that stores instructions and data, such as in-circuit programming and user code, and input/output ports and related structure for exchanging data with an external device. Using in-circuit programming code stored on the chip, the chip interactively establishes an in-circuit programming exchange with an external device to update data and instructions including the in-circuit programming code. Input/output conflicts during in-circuit programming can be avoided by employing a memory controller to handle at least part of the in-circuit programming operations. The memory controller allows the in-circuit programming code to be updated in real time.

Abstract: A wear leveling method for a flash is provided, wherein the flash memory includes a plurality of physical blocks grouped into at least a data area and a spare area. The method includes setting a first predetermined threshold value as a wear-leveling start value and randomly generating a random number as a memory erased count, wherein the random number is smaller than the wear-leveling start value. The method also includes counting the memory erased count each time when the physical blocks are erased and determining whether the memory erased count is smaller than the wear-leveling start value, wherein a physical blocks switching is performed between the data area and the spare area when the memory erased count is not smaller then the wear-leveling start value. Accordingly, it is possible to uniformly use the physical blocks, so as to effectively prolong a lifetime of the store system.

Abstract: Network arrangements wherein a network interface receives write requests of files of a file system from a client computer, each file including respective data and respective metadata. A processor registers the metadata of a file to at least one first type storage medium and writes the data of the file to the at least one second type storage medium based on file value information. The storage system stores information of address ranges of an integrated logical unit, in which each address range corresponds to the at least one first type storage medium and the at least one second type storage medium included in the integrated logical unit, and provides the information of address ranges of the integrated logical unit to the client computer.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: Methods and systems provide recognition of a device in a daisy chain cascade configuration. Input circuitry at a device receives an input signal that indicates device configuration following a power-up, reset or other operation of the device. A pulse generator generates a pulse in response to the operation, the pulse occurring while the input signal indicates device configuration. A state latch register stores the state of the input signal in response to the received pulse, thereby storing a state indicating configuration of the respective device. Following this operation, the input circuitry may receive signals unrelated to the device configuration, thereby obviating the need for additional pin assignment.

Abstract: A network device determines the presence of the pre-specified string in a message based on a sequence matching rule. A sequence represents non-contiguous portions of the message. A combination of content addressable memory, programmable processing units, and the programmable control unit may determine the presence of the pre-specified string in the message by comparing the non-contiguous portions of the message. Such an approach may reduce the computational resources required for searching the pre-specified string in the message.

Abstract: Data units are prefetched into a cache memory by executing a first prefetch task to prefetch a first prefetch series of data units from off-cache. A first prefetch operation is executed to prefetch and store a first selected set of data units. Decisions are made about the first prefetch task, subsequent prefetch operations and prefetch tasks based on in-cache data units associated with the first prefetch task and on other data units that are read from off-cache but that are not associated with the first prefetch task. A determination is made whether an additional data unit that is read from an off-cache logical location is a first prefetch series member. If so, it is associated with the first prefetch task, and, for decision making, is treated as having been prefetched into cache in accordance with the first prefetch task.

Abstract: A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For example, with separate files of the size 32×32 supported configurations of 128×32 bit s, 64×64 bit s and 32×128 bit s can be in operation each cycle. Single width, double width, quad width operands are optimally supported without increasing the register file size and without increasing the number of register file read or write ports.

Abstract: An information processing apparatus for recording data onto a recording medium, includes an access controller for outputting, to a medium-specific controller, record data input from an application and directed to the recording medium. The access controller performs a read-modify-write (RMW) operation by verifying whether one of a record start position and a record end position of the record data input by a logical sector unit from the application is different from a delimitation position of a physical sector as an access unit of the recording medium, acquiring the record data by the physical sector unit and storing the record data onto a memory if one of the record start position and the record end position is different from the delimitation position, updating logical sector data as part of stored physical sector data with the input record data, and outputting the updated physical sector data to the medium-specific controller.

Abstract: A data storage device mirrors data on a data storage medium. The multiple instances of data are synchronized in order to optimize performance of the reading and writing, and the integrity of the data. Preferably, a data storage device is allowed to defer writing multiple copies of data until a more advantageous time.