Abstract: Configuring processors in a target system includes' prompting a user to select workload units to use in the configuration, prompting the user to input a quantity of processing power required in terms of partition workload capacity required, obtaining a system work capacity for the target system in the appropriate units from a look-up table, and calculating the number of partition processors. The number of partition processors equals the total number of system processors, times the partition workload capacity divided by the system work capacity. The calculated number of partition processors is tested to see if it is within a predetermined percentage of the next full processor increment. If within the predetermined percentage, then using dedicated processors is recommended, otherwise using shared processors is recommended. The calculated number of partition processors and the recommended use of shared or dedicated processors is displayed to the user for validation or changing of the values.

Abstract: A system and method provide a computer-based automated tool for quickly and efficiently designing utility stations. One example of such a utility station is a unit substation. The tool includes a database of user-selective predrawn symbols that are associated with a pre-defined and stored station template. Each of the respective symbols have associated therewith attributes that are computer recognizable as being attributes associated with the respective symbols, and may be combined into a list, when the symbols are selected for use with the station. The tool presents a graphical rendering of the symbols arranged on the station, after the respective symbols have been identified.

Abstract: A new method is presented for generating a probability map, a cutoff map, and a confidence limit map in one single operation. In addition, the new method can also generate a cube representing a cubic volume of earth formation by using the same method for generating the aforementioned maps.

Abstract: The invention uses foam blocks in commercially available sizes to build curved structure that are used in constructing habitable buildings. The curved structure is divided into sections using a Computer Assisted Drafting program. The foam blocks are cut to the curvature of the curved structure by a Computer Assisted Manufacturing program. The blocks are joined and then coated with a high strength coating to create the curved structure.

Abstract: A broker for the management of client requests issued by a client computer over a client-server network. Depending on its availability of resources, the broker determines whether to respond to the client request, or hand-off the client request to another server. The broker supports a virtual connection between the client and the other server, without interfering with communication protocols or disrupting client requests. The other server fulfills client requests by operating in place of the broker. The server terminates the virtual connection when all client requests have been completely fulfilled.

Abstract: A method determines approximate probabilities of states of a system represented by a model. The model includes nodes connected by links. Each node represents possible states of a corresponding part of the system, and each link represents statistical dependencies between possible states of related nodes. The nodes are grouped into arbitrary sized clusters such that every node is included in at least one cluster and each link is completely contained in at least one cluster. Messages, based on the arbitrary sized cluster, are defined. Each message has associated sets of source nodes and destination nodes, and a value and a rule depending on other messages and on selected links connecting the source nodes and destination nodes. The value of each message is updated until a termination condition is reached. When the termination condition is reached, approximate probabilities of the states of the system are determined from the values of the messages.

Abstract: In one embodiment, a method for specifying addressability in a memory-mapped device is disclosed. A data access primitive is used to model addressablity for the memory-mapped device. Addressability comprises an address matching function, a lane matching function and one or more bus connections. A first starting address for the memory-mapped device is specified. A first set of addressing matching function, lane matching function and one or more bus connections for the memory-mapped device is generated using the data access primitive and the first starting address.

Abstract: A device for simulating circuits is provided with an identifying system and a verifying system. The identifying system identifies a pair of wires in which two signals operate simultaneously within an appointed period and a pair of wires in which two signals do not operate almost simultaneously within the appointed period. The verifying system verifies actions of a circuit to be analyzed, under an assumption that the coupling capacitor between the pair of wires in which it is judged by the identifying system that two signals do not simultaneously operate within the appointed period is a ground capacitor.

Abstract: A method is disclosed for designing an energy-absorbing impact zone for a vehicle interior, including acquiring test data representative of an occupant, determining a force versus deflection curve for the vehicle impact zone, analyzing the force versus deflection curve, and utilizing the analysis to adjust the stiffness of the energy-absorbing impact zone and to shape the force versus deflection curve so that a constant area under the force versus deflection curve has the minimum deflection possible without exceeding a certain force limit and a certain head impact criterion.

Abstract: A method and device emulate the features of a EEPROM memory device. The device is included into a memory macrocell which is embedded into an integrated circuit comprising also a microcontroller. The device includes a Flash EEPROM memory structure formed by a predetermined number of sectors wherein at least two sectors of the Flash memory structure are used to emulate EEPROM byte alterability.

Abstract: A system and method for developing a reusable electronic circuit design module are presented in various embodiments. In one embodiment, the functional design elements comprising a design module are entered into a database along with documentation elements that describe the design elements. The functional design elements are linked with selected ones of the documentation elements in the database. A testbench is simulated with the design module, and the generated results are stored in a database and linked with the functional design elements. By linking the simulation results, documentation, and design elements, the characteristics of the design module are easily ascertained by a designer who is reusing the design module.

Abstract: A method and system is provided for determining the progress toward the achievement of best-in-class motor vehicles. The method may be comprised of several steps. First, internal organizational data is gathered. [The internal organizational data includes critical design characteristics, critical manufacturing characteristics, and critical performance characteristics. The critical design characteristics are those design features which are historically valued by customers. The critical manufacturing characteristics are those manufacturing features which are have also been valued by customers. The critical performance characteristics are those performance characteristics valued by customers.] Second, external organizational data is gathered. [The external organizational data includes a list of design characteristics and manufacturing characteristics that are deemed important by suppliers and competitors.

Abstract: A system and method of generating a finite element mesh for a threaded fastener and joining structure assembly includes a computer system for generating a mesh model of the threaded fastener and joining structure assembly by creating nodes and elements for each non-threaded portion of the threaded fastener and joining structure assembly using cylindrical coordinates and creating nodes and elements for each threaded portion of the threaded fastener and joining structure assembly using helical coordinates. The system and method also includes a user evaluating the mesh model of the threaded fastener and joining structure assembly using finite element analysis and evaluating a result of the finite element analysis using a visualization software program and a computer system. The system and method further includes a user predicting a stress of the threaded fastener and joining structure assembly from the evaluation of the result of the finite element analysis.

Abstract: Access privileges for a user are provided in a performance evaluation system by storing an organizational structure for an enterprise, a view and a class of services for the user. The organizational structure includes a plurality of levels and a plurality of members assigned to the levels. The view specifies the levels and the members of the organizational structure to which the user is allowed access. The class of services specify services of the performance evaluation system that the user is allowed to perform. The user has access privileges to perform services within the class of services for levels and members within the view.

Abstract: A system and method for simulating network connection characteristics by alteration of a network packet. In general, the method of the present invention includes providing a driver that is capable of accessing all outgoing and incoming network packets and altering a network packet to simulate a connection characteristic of the network. In particular, the method of the present invention includes receiving a network packet, assigning a new, simulated network address to the network packet and performing modification of the network packet to simulate certain network connection characteristics (including, for example, transmission delay, limited bandwidth, packet dropping, packet fragmentation, packet duplication and packet reordering). The system of the present invention includes a modification module for altering certain characteristics of a packet.

Abstract: A system and method for bulk transfer to and from the SRAMs in which a starting memory address is latched and is then incremented every clock cycle to generate a new memory address. The addresses are decoded and memory requests are pipelined to the SRAM memory, one every clock cycle. When the memory controller detects transfer of the boundary of a predetermined number of clock cycles or words (e.g. 64 words or four clock cycles) the burst mode of data transfer is stopped and the memory controller waits for a “done” signal before resuming another cycle of the burst transfer mode. The memory controller on detecting a request on this address boundary first does a memory refresh followed by a requested operation; e.g. a continuation of the transfer operation.

Abstract: Restructuring a CAD-system generated design model includes receiving at a computer a command to restructure the design model. The command to restructure indicates a desired change in a hierarchical relationship of a first subset of the model's components with respect to other model components. In accordance with the command to restructure, a new hierarchical data structure can be generated. The new hierarchical data structure identifies a new hierarchical relationship between the model components. Other relationships that are changed as a result of the command to restructure are also determined and are automatically preserved subsequent to the generation of the new hierarchical relationship.

Abstract: Methods, apparatus and computer program products for modeling integrated circuits having dense devices therein that experience linewidth (e.g., gate electrodes) reductions during fabrication are provided. For dense devices having electrical paths therein and first and second gate electrodes that overlie the electrical path, operations include determining an electrical gate length of the first gate electrode by evaluating a change in current through the electrical path relative to a change in gate length of the second gate electrode. The operation to determine the electrical gate length of the first gate electrode includes evaluating a change in simulated drain-to-source current through the electrical path relative to a change in the electrical gate length of the second gate electrode.

Abstract: A methods and systems for capacity planning of server resources are described wherein a load simulation tool is used to use actual data gathered from a server cluster during operation to simulate server cluster operation in which the load (requests per second) can be increased, and the effects on the utilization of resources can be observed. Plans containing recommendations are then presented to a system user so the user can make decisions necessary regarding whether to change configuration hardware to meet expected load increases in the future.

Abstract: This system represents a customizable simulation model of an ATM/SONET Framer for System Level Verification and Performance-Characterization. An Asynchronous Transfer Mode (ATM) data processing ASIC interfaces with a Media Access Control (MAC) device that presents an electrical data path interface, called Universal Test & Operations PHY Interface for ATM (UTOPIA), using ATM protocol on the ASIC side and simplex optical interfaces using Synchronous Optical Network (SONET) protocol on the network side. Such a MAC device, commonly referred to as ATM/SONET Framer, provides one Receive and one Transmit interface to the network at various SONET line rates such as 155.52 Mbps (OC-3), 622.08 Mbps (OC-12), 2488.32 Mbps (OC-48), etc. The ATM and the SONET interfaces operate on different clock frequencies and thus represent two distinct clocking domains. The data interchange between the two clocking domains is achieved via FIFO buffer elements and associated control and status signals.