Patents Examined by Kevin M. Picardat
  • Patent number: 10388684
    Abstract: An image sensor package may include a semiconductor wafer having a pixel array, a color filter array (CFA) formed over the pixel array, and one or more lenses formed over the CFA. A light block layer may couple over the semiconductor wafer around a perimeter of the lenses and an encapsulation layer may be coupled around the perimeter of the lenses and over the light block layer. The light block layer may form an opening providing access to the lenses. A mold compound layer may be coupled over the encapsulation layer and the light block layer. A temporary protection layer may be used to protect the one or more lenses from contamination during application of the mold compound and/or during processes occurring outside of a cleanroom environment.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: August 20, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Larry Duane Kinsman, Swarnal Borthakur, Marc Allen Sulfridge, Scott Donald Churchwell, Brian Vaartstra
  • Patent number: 10374132
    Abstract: A method of manufacturing a wavelength conversion member with improved capability of releasing heat from a fluorescent material is provided. The method of manufacturing the wavelength conversion member includes: disposing a fluorescent material paste containing a fluorescent material and a binder on a surface of a light-transmissive body; orienting face-down the surface where the fluorescent material paste is disposed, to settle the fluorescent material in the fluorescent material paste on a side opposite to another side of the fluorescent material paste, the another side being in contact with the light-transmissive body; and curing the binder in a state where the fluorescent material has been settled, to form a fluorescent material layer.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: August 6, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Masami Kumano, Yuji Sato
  • Patent number: 10358340
    Abstract: Integrated circuits having shielded micro-electromechanical system (MEMS) devices and method for fabricating shielded MEMS devices are provided. In an example, an integrated circuit having a shielded MEMS device includes a substrate, a ground plane including conductive material over the substrate, and a dielectric layer over the ground plane. The integrated circuit further includes a MEMS device over the ground plane. Also, the integrated circuit includes a conductive pillar through the dielectric layer and in contact with the ground plane. The integrated circuit includes a metallic thin film over the MEMS device and in contact with the conductive pillar, wherein the metallic thin film, the conductive pillar and the ground plane form an electromagnetic shielding structure surrounding the MEMS device. Further, the integrated circuit includes an acoustic shielding structure over the substrate and adjacent the electromagnetic shielding structure.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: July 23, 2019
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Humberto Campanella-Pineda, Rakesh Kumar, Zouhair Sbiaa, Nagarajan Ranganathan, Ramachandramurthy Pradeep Yelehanka
  • Patent number: 10361170
    Abstract: A semiconductor package including a first substrate including first upper pads, the first upper pads on a top surface of the first substrate, a second substrate including second upper pads, the second upper pads on a top surface of the second substrate, a pitch of the second upper pads being less than a pitch of the first upper pads, and a first semiconductor chip on and electrically connected to both (i) at least one of the first upper pads and (ii) at least one of the second upper pads may be provided.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungeun Pyo, Jongbo Shim, Ji Hwang Kim, Chajea Jo, Sang-Uk Han
  • Patent number: 10347783
    Abstract: Various examples are provided for hot carrier spectral photodetectors that can be tuned. In one example, among others, a hot-carrier photodetector includes a graded barrier; an absorber disposed on the graded barrier; and a second barrier disposed on the absorber. For example, the absorber can include p-type doped GaAs. The graded barrier is disposed between the absorber and an injector, which can include p-type doped GaAs. In some implementations, the hot-carrier detector can include multiple barriers and absorbers. The hot-carrier photodetector can include an optical source (e.g., a LED) to trigger the VLWIR response in the photodetector.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: July 9, 2019
    Assignee: Georgia State University Research Foundation, Inc.
    Inventors: A. G. Unil Perera, Yanfeng Lao
  • Patent number: 10347700
    Abstract: A flexible display device includes a protection member, a first adhesion member, a display member, a second adhesion member, and a window member. A thickness of the display member is less than a sum of thicknesses of the protection member and the window member. The display member includes a display panel layer, a touch sensing layer, and a reflection prevention layer integrated with each other to reduce a thickness of the flexible display device. The reduction in thickness enables the flexible display device to be bent with a relatively small radius of curvature, as well as to be repeatedly bent (or otherwise flexed) with reduced potential for delamination of the first and second adhesion members.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 9, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Taehoon Yang, Yongsu Lee, Sungchul Kim, Sunghoon Kim, Sungsik Yun, Kyoungah Lee
  • Patent number: 10340279
    Abstract: Semiconductors and methods of manufacturing semiconductors are provided. A semiconductor can include a plurality of insulating layers, and a plurality of conductive layers, with the insulating layers and the conductive layers alternately stacked. A plurality of through electrodes penetrate the conductive layers. At least some the through electrodes are electrically connected to one of the conductive layers. In addition, different conductive layers are connected to different through electrodes. A method of forming a semiconductor structure includes providing a plurality of antifuses, wherein each of the through electrodes is separated from each of the conductive layers by an antifuse. The method further includes supplying at least a first voltage to a first through electrode while applying less than a second voltage to the other electrodes, wherein the first voltage is greater than the second voltage.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: July 2, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Tsunenori Shiimoto
  • Patent number: 10340153
    Abstract: A fan-out semiconductor package includes a redistribution layer, an interconnection member, a semiconductor chip, and a protective layer. The interconnection member has a through hole disposed on the redistribution layer. The semiconductor chip is disposed on the redistribution layer exposed within the through hole. The protective layer is formed between the redistribution layer and the interconnection member, and coupled to the interconnection member to protect the interconnection member.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hong Won Kim, Tae Sung Jeong
  • Patent number: 10319743
    Abstract: A novel semiconductor device or display device is provided. A semiconductor substrate is used as a substrate of a display portion and a transistor in the display portion is formed using the semiconductor substrate. In this way, variation in the characteristics of the transistors among pixels is reduced and pixel density can be increased. Moreover, transistors used for a driver circuit, a signal generation circuit, and a level shifter are formed using the semiconductor substrate. As a result, these circuits can be formed directly on the substrate of the display portion, whereby bonding of a chip and the substrate is unnecessary. Furthermore, these circuits can be easily connected to each other, so that signal delay or an increase in power consumption due to complicated wirings can be prevented.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: June 11, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 10319845
    Abstract: An insulated gate bipolar transistor and a method for fabricating the insulated gate bipolar transistor are provided. The insulated gate bipolar transistor includes a semiconductor layer including a bulk layer and a cell region including a first region and a second region. The insulated gate bipolar transistor also includes a well region, a drift region, and a plurality of gate structures in the bulk layer associated with the cell region. Further, the insulated gate bipolar transistor includes source and drain doped regions and an ohmic contact region in a top region of the well region. A size of the source and drain doped regions in the second region is smaller than a size of the source and drain doped regions in the first region. A size of the ohmic contact region in the second region is larger than a size of the ohmic contact region in the first region.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: June 11, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Jian Liu
  • Patent number: 10312100
    Abstract: A conductor including a graphene layer and a method of manufacturing the conductor are provided. The conductor may further include a nano pattern disposed on a substrate, and the graphene layer may be formed on the nano pattern. The nano pattern may have any various shapes and include a material that interacts with the graphene layer. The nano pattern and the graphene layer included in the conductor may interact with each other, such that the electric characteristics of the conductor are maintained while the heat transfer characteristics thereof are improved.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: June 4, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Wonhee Ko, Hyowon Kim, Jiyeon Ku, Donggyu Kim, Seunghwa Ryu, Seongjun Jeong
  • Patent number: 10304967
    Abstract: A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: May 28, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Archana Venugopal, Luigi Colombo, Arup Polley
  • Patent number: 10304767
    Abstract: An object of the present invention is to improve the degree of freedom in the wiring design of a wiring substrate configuring a semiconductor device. Lands having an NSMD structure and a land-on-through-hole structure are arranged at positions not overlapping with a plurality of leads arranged on a chip loading surface of a wiring substrate in transparent plan view on the outer peripheral side of a mounting surface of the wiring substrate configuring a semiconductor device having a BGA package structure. On the other hand, land parts having the NSMD structure and to which lead-out wiring parts are connected are arranged at positions overlapping with the leads arranged on the chip loading surface of the wiring substrate in transparent plan view on the inner side than the group of lands in the mounting surface of the wiring substrate.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: May 28, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuya Kobayashi
  • Patent number: 10304832
    Abstract: Disclosed are integrated circuit (IC) structure embodiments that incorporate stacked pair(s) of field effect transistors (FETs) (e.g., gate-all-around FETs), including a lower FET and an upper FET on the lower FET, and various metal components that enable power and/or signal connections to the source/drain regions of those FETs. The metal components can include first buried wire(s) within an isolation region in a level below the stacked pair and a first embedded contact that electrically connects a source/drain region of the lower FET to a first buried wire. Optionally, the metal components can also include second buried wire(s) in dielectric material at the same level as the upper FET and a second embedded contact that electrically connects a source/drain region of the upper FET to a second buried wire. Also disclosed are embodiments of a method of forming such IC structure embodiments.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: May 28, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel Chanemougame, Lars Liebmann, Ruilong Xie
  • Patent number: 10304861
    Abstract: The present disclosure provide an array substrate and a method of manufacturing the same, and a display panel. The array substrate includes: a base substrate; a first signal transmission layer comprising a common electrode line; a first insulating layer covering the first signal transmission layer and having a first through hole at a position corresponding to the common electrode line; a first electrode layer located on the first insulating layer, the first electrode layer comprising a connection electrode located at the position of the first through hole; a second insulating layer covering the first electrode layer and having a second through hole at a position corresponding to the connection electrode; and a second electrode layer comprising a common electrode that covers the second through hole; the connection electrode contacts the common electrode line and the common electrode respectively.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: May 28, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Shoukun Wang, Jianfeng Yuan, Huibin Guo, Yuchun Feng, Liangliang Li, Tsung-Chieh Kuo
  • Patent number: 10304909
    Abstract: A display device includes a substrate, first and second data lines, and first and second sub-pixel units. The first sub-pixel unit includes a first electrode and a first light emitting layer disposed on the first electrode. The first electrode has a first region with a first area overlapping the first data line. The second sub-pixel unit includes a second electrode and a second light emitting layer disposed on the second electrode. The second electrode has a second region with a second area overlapping the second data line, wherein the first area is greater than the second area. The luminescence color of the first light emitting layer and the luminescence color of are different, and the luminescence color of the first light emitting layer is blue.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 28, 2019
    Inventors: Chandra Lius, Kuan-Feng Lee, Chung-Wen Yen, Chao-Hsiang Wang
  • Patent number: 10304827
    Abstract: Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: May 28, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Fred Salzman, Bradley David Sucher
  • Patent number: 10290553
    Abstract: Provided is a method for determining and utilizing process completion of post heat treatment (PHT) of a dry etch process, the method comprising: providing a substrate in a process chamber, the substrate having a film layer and an underlying layer, the film layer having one or more regions; performing a dry etch process to remove the film layer or region of the film layer, the dry etch process generating a byproduct layer; measuring one or more properties of the byproduct layer; adjusting the PHT process based on the measured one or more properties of the byproduct layer; and performing the PHT process to remove the byproduct layer on the substrate; wherein the PHT process utilizes a real time in-situ process to concurrently determine when removal of the byproduct layer is complete.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 14, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Jacob Theisen, Aelan Mosden
  • Patent number: 10290784
    Abstract: An optoelectronic semiconductor component comprises an optoelectronic semiconductor chip (C1) having an electrically conductive substrate (T), an active part (AT) containing epitaxially grown layers, and an intermediate layer (ZS) which is arranged between the substrate (T) and the active part (AT) and contains a solder material. The optoelectronic semiconductor component further comprises an electrical connection point, which at least partially covers an underside of the substrate (T), wherein the electrical connection point comprises a first contact layer (KS1) on a side facing the substrate (T), and the first contact layer (KS1) contains aluminium or consists of aluminium.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: May 14, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Korbinian Perzlmaier, Stefanie Rammelsberger, Anna Kasprzak-Zablocka, Julian Ikonomov, Christian Leirer
  • Patent number: 10283526
    Abstract: Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop are disclosed. In one aspect, a standard cell circuit is provided that employs active devices that include corresponding gates disposed with a gate pitch. First and second voltage rails having a line width are disposed in a first metal layer. Employing the first and second voltage rails having substantially a same line width reduces the height of the standard cell circuit as compared to conventional standard cell circuits. Metal lines are disposed in a second metal layer with a metal pitch less than the gate pitch such that the number of metal lines exceeds the number of gates. Electrically coupling the first and second voltage rails to the metal shunts increases the conductive area of each voltage rail, which reduces a voltage drop across each voltage rail.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 7, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: John Jianhong Zhu, Jeffrey Junhao Xu, Mustafa Badaroglu