Abstract: The embodiments of present disclosure provide a thin film transistor, a method for manufacturing the same, and an array substrate. The thin film transistor comprises an active layer provided on a substrate, the active layer including a middle channel region, a first high resistance region and a second high resistance region provided respectively on external sides of the middle channel region, a source region provided on an external side of the first high resistance region and a drain region provided on an external side of the second high resistance region, wherein a base material of the active layer is diamond single crystal.

Abstract: An array substrate and a display apparatus are provided according to embodiments of the disclosure. A pixel unit includes a first sub-pixel electrode and a second sub-pixel electrode, the first sub-pixel electrode is connected to a drain of the first TFT, and the second sub-pixel electrode is connected to a drain of the second TFT, a resistance between a source of the first TFT and the data line connected to the first TFT is greater than a resistance between a source of the second TFT and the data line connected to the second TFT, and/or, a resistance between the drain of the first TFT and the first sub-pixel electrode is greater than a resistance between the drain of the second TFT and the second sub-pixel electrode.

Abstract: Provided is a package device, relating to the technical field of lamp beads. The package device comprises an SMD holder, wherein the SMD holder is a hollow housing with one end opened; and the material of sidewalls of the SMD holder is transparent plastic. In the package device provided by the present invention, a transparent material is provided as the material of the sidewalls of the SMD holder, and light generated after a chip is powered on can be partially transmitted out through the sidewalls of the SMD holder, avoiding blocking of the light generated after the chip is powered on by the sidewalls of the SMD holder, thereby increasing transmittance of light from the chip.

Abstract: A semiconductor device of an embodiment includes a p+-type region selectively disposed in a surface of an n-type silicon carbide epitaxial layer disposed on an n+-type silicon carbide substrate, an element structure that includes a source electrode and a p+-type region that form a metal-semiconductor junction on the n-type silicon carbide epitaxial layer, a p?-type region and another p?-type region that surround the periphery of the element structure, and an n+-type channel stopper region that surrounds the periphery of the p?-type regions so that the n-type silicon carbide epitaxial layer is therebetween. The n+-type channel stopper region has a second n+-type channel stopper region whose impurity concentration is high, and a first n+-type channel stopper region that encompasses the second n+-type channel stopper region and whose impurity concentration is lower than that of the second n+-type channel stopper region.

Abstract: A compound semiconductor substrate according to the present invention includes a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, wherein the ground substrate is formed of a sintered body, the seed layer is formed of a single crystal, the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, and an FWHM of an X-ray diffraction peak of the buffer layer obtained by an X-ray diffraction rocking curve measurement is 800 arcsec or less.

Abstract: This disclosure provides a package substrate which includes: a first conductive layer having a first conductive area and a second conductive area; a package unit layer disposed on the first conductive layer and including a first circuit device having a first terminal connected to the first conductive area and a second terminal connected to the second conductive area, a first conductive pillar connected to the first conductive area, and an encapsulant material; and a second conductive layer disposed on the package unit layer and having a first metal wire connected to the first conductive pillar.

Abstract: A fin of silicon-germanium material is formed and covered with an epitaxially grown layer of silicon material. A dummy transistor gate is then formed to extend over a channel of the fin. Sidewall spacers are formed on each side of the dummy transistor gate and directly on top of the expitaxial silicon layer. Epitaxially grown raised source and drain regions are formed on each side of the dummy transistor gate adjacent the sidewall spacers. The dummy transistor gate and a portion of the epitaxial silicon layer (underneath said dummy transistor gate) are removed and replaced by a metal gate.

Abstract: A method includes forming at least one fin above a semiconductor substrate. An isolation structure is formed adjacent the fin. A liner layer is formed above the isolation structure adjacent an interface between the fin and the isolation structure. The liner layer includes a material different than the isolation structure. A sacrificial gate structure is formed above a portion of the fin and includes a sacrificial gate insulation layer and a sacrificial gate structure. The sacrificial gate structure is removed. The sacrificial gate insulation layer is removed selectively to the liner layer. A replacement gate structure is formed above a portion of the fin in a cavity defined by removing the sacrificial gate structure.

Abstract: A method of fabricating a microelectronic device comprising providing a substrate comprising a first bottom surface, providing a mold comprising a first top surface with first projections, and punching the first projections through the first bottom surface to define anchors, pre-cantilevers, and cavities in the substrate. A piezoelectric cantilever actuator system array prepared by a process comprising the steps of providing a substrate comprising a first bottom surface, providing a mold comprising a first top surface with first projections, and punching the first projections through the first bottom surface to define anchors, pre-cantilevers, and cavities in the substrate. A microelectronic device comprising a base, a first anchor coupled to the base, and a first cantilever coupled to the first anchor, wherein the base, the first anchor, and the first cantilever are an integral structure formed from the same substrate material.

Abstract: A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.

Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes a first semiconductor die, a package substrate underlying the first semiconductor die, an interposer between the package substrate and the first semiconductor die, and a second semiconductor die between the package substrate and the interposer. The semiconductor die assembly further comprises a heat spreader including a cap thermally coupled to the first semiconductor die at a first elevation, and a pillar thermally coupled to the second semiconductor die at a second elevation different than the first elevation. The heat spreader is configured to transfer heat away from the first and second semiconductor dies via the cap and the pillar, respectively. The interposer extends around at least 75% of a perimeter of the pillar in a plane between the first and second elevations.

Abstract: Various embodiments provide a thin film transistor (TFT), a fabrication method thereof, and a display apparatus including the TFT. A carbon nanotube layer is formed over a substrate. The carbon nanotube layer includes a first plurality of carbon nanotubes. A plurality of gaps are formed through the carbon nanotube layer to provide a first patterned carbon nanotube layer. Carbon nanotube structures each including a second plurality of carbon nanotubes are formed in the plurality of gaps. The carbon nanotube structures have a carrier mobility different from the first patterned carbon nanotube layer, thereby forming an active layer for forming active structures of the thin-film transistor.

Abstract: An image sensor includes a pixel array having plurality of pixel cells arranged into a plurality of rows and a plurality of columns of pixel cells in a first semiconductor die. A plurality of pixel support circuits are arranged in a second semiconductor die that is stacked and coupled together with the first semiconductor die. A plurality of interconnect lines are coupled between the first and second semiconductor dies, and each one of the plurality of pixel cells is coupled to a corresponding one of the plurality of pixel support circuits through a corresponding one plurality of interconnect lines. A plurality of shield bumps are disposed proximate to corners of the pixel cells in the pixel array and between the first and second semiconductor dies such that each one of the plurality of shield bumps is disposed between adjacent interconnect lines along a diagonal of the pixel array.

Abstract: An ultra-high voltage device is provided. The ultra-high voltage device includes a substrate, a first well zone formed in the substrate, a second well zone having a surface formed in the substrate adjacent to the first well zone, a gate oxide formed on the first well zone and the second well zone of the substrate, a gate formed on the gate oxide, a channel formed in the first well zone underneath the gate oxide, an accumulation region formed in the second well zone underneath the gate oxide adjacent to the channel, wherein only a part of the accumulation region is implanted with a dopant to form an implant region therein, and an insulation region formed on the surface of the second well zone of the substrate adjacent to the accumulation region, wherein a boundary is formed between the insulation region and the accumulation region.

Abstract: For a purpose of raising the breakdown voltage of a semiconductor device, the creepage distance and clearance between an electrode terminal and another metallic portion are preferably increased. A semiconductor device is provided, the semiconductor device including: a semiconductor element; a case portion that houses the semiconductor element; and an external terminal provided to a front surface of the case portion, wherein the front surface of the case portion has, formed thereon: a wall portion that protrudes from the front surface; and a hollow portion that is provided to a region surrounded by the wall portion and is depressed relative to the front surface, and the external terminal is arranged on a floor surface of the hollow portion.

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and strained source and drain regions is described. The at least one gate structure is disposed over the substrate and on the isolation structures. The spacers are disposed on sidewalls of the at least one gate structure. First blocking material layers are disposed on the spacers. The strained source and drain regions are disposed at two opposite sides of the at least one gate structure. Second blocking material layers are disposed on the strained source and drain regions. The first and second blocking material layers comprise oxygen-rich oxide materials.

Abstract: A method and structure, the structure having a substrate, an active device in an active device semiconductor region; of the substrate, a microwave transmission line, on the substrate, electrically connected to the active device, and microwave energy absorbing “dummy” fill elements on the substrate. The method includes providing a structure having a substrate, an active device region on a surface of the structure, an ohmic contact material on the active device region, and a plurality of “dummy” fill elements on the surface to provide uniform heating of the substrate during a rapid thermal anneal process, the ohmic contact material and the “dummy” fill elements having the same radiant energy reflectivity. The rapid thermal anneal processing forms an ohmic contact between an ohmic contact material and the active device region and simultaneously converts the “dummy” fill elements into microwave lossy “dummy” fill elements.

Abstract: An image sensor may include: a photoelectric conversion element suitable for generating a photo charge in response to incident light; and a transfer transistor suitable for transferring the photo charge generated by the photoelectric conversion element to a floating diffusion in response to a transfer signal, the transfer transistor comprising a first transfer gate formed over the photoelectric conversion element; an opening formed in the first transfer gate and exposing the photoelectric conversion element; a second transfer gate formed in the opening; and a channel layer interposed between the first and second transfer gates and between the photoelectric conversion element and the second transfer gate.

Abstract: Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.

Abstract: Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.