Abstract: The present disclosure relates to semiconductor based Josephson junctions and their applications within the field of quantum computing, in particular a tuneable Josephson junction device has been used to construct a gateable transmon qubit. One embodiment relates to a Josephson junction comprising an elongated hybrid nanostructure comprising superconductor and semiconductor materials and a weak link, wherein the weak link is formed by a semiconductor segment of the elongated hybrid nanostructure wherein the superconductor material has been removed to provide a semiconductor weak link.

Abstract: A semiconductor material includes a compositionally-graded transition layer, an intermediate later and a gallium nitride material layer. The compositionally-graded transition layer has a back surface and a top surface, and includes a gallium nitride alloy. The gallium concentration in the compositionally-graded transition layer increases from the back surface to the front surface. The intermediate layer is formed under the compositionally-graded transition layer. The gallium nitride material layer is formed over the compositionally-graded transition layer, and has a crack level of less than 0.005 ?m/?m2.

Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.

Abstract: The devices can be fabricated by a method that permits active polymer chains to be polymerized on the surface of an electrode such that the active polymer chains are aligned with one another. The active polymer chains can also be covalently linked to a second electrode so the active polymer chains are located in an active layer of the device. The polymerization method can be paused and resumed at any point in the polymerization so nanoparticles can be added into the active layer. Additionally, the polymerization method allows that active polymer chains to be polymerized so they include junctions such as p-n junctions and Schottky junctions.

Abstract: A semiconductor structure includes a source drain region of a first material and an extension region of a second material. A semiconductor device fabrication process includes forming a sacrificial dielectric portion upon a semiconductor substrate, forming a sacrificial gate stack upon the sacrificial dielectric portion, forming a gate spacer upon the sacrificial dielectric portion against the sacrificial gate, forming a source drain region of a first doped material upon the semiconductor substrate against the gate spacer, forming a replacement gate trench by removing the sacrificial gate stack, forming an extension trench by removing the sacrificial dielectric portion, and forming an extension region of a second doped material within the extension trench.

Abstract: There is provided a semiconductor device provided with a metal base, a frame-shaped resin case adhered to the metal base, a semiconductor chip having a main electrode and being disposed inside the resin case, a main terminal having an internal end which is electrically connected to the main electrode of the semiconductor chip, integrally fixed to the resin case, and exposed inside the resin case and an external end exposed outside the resin case, a heat dissipation member which is placed, in contact with the metal base, between the metal base and the internal end of the main terminal, and has higher thermal conductivity than that of the resin case.

Abstract: A semiconductor package. The semiconductor package includes a first side, a second side, a molded substrate, a die, and a lead frame. The second side of the semiconductor package is opposite the first side of the semiconductor package. The die and lead frame are embedded into the molded substrate. The lead frame is also positioned between the first side and the second side of the semiconductor package to provide a first electrical connection between the first side and the second side of the semiconductor package.

Abstract: An example circuit includes: one or more power rails and a tap cell structure. The tap cell structure includes one or more decoupling capacitor cells and one or more tap cells. The one or more tap cells are electrically coupled to the one or more power rails. The one or more decoupling capacitor cells are disposed adjacent to the tap cells and electrically coupled to the one or more power rails.

Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.

Abstract: The present disclosure relates to a micro-fluidic probe card that deposits a fluidic chemical onto a substrate with a minimal amount of fluidic chemical waste, and an associated method of operation. In some embodiments, the micro-fluidic probe card has a probe card body with a first side and a second side. A sealant element, which contacts a substrate, is connected to the second side of the probe card body in a manner that forms a cavity within an interior of the sealant element. A fluid inlet, which provides a fluid from a processing tool to the cavity, is a first conduit extending between the first side and the second side of the probe card body. A fluid outlet, which removes the fluid from the cavity, is a second conduit extending between the first side and the second side of the probe card body.

Abstract: Methods of patterning a target material layer are provided herein. The method includes steps of positioning a semiconductor wafer having the target material layer thereon in an etch chamber and of providing a flow of etch gases into the etch chamber, the flow of etch gases etchant gas comprising a plurality of gases. The semiconductor wafer has a patterned hardmask feature formed from a compound on the target material layer. The method also includes steps of etching the target material layer using the patterned hardmask feature as a mask feature, wherein one of the gases chemically alters the patterned hardmask feature and at least one of the gases chemically repairs the patterned hardmask feature so that the patterned hardmask feature retains its dimensions during the etching. Associated semiconductor wafer are also provided herein.

Abstract: A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides of the first and second dies may each face the interposer. A bond wire may electrically connect the first die to the second side of the interposer and a bond wire may electrically connect the second die to the first side of the interposer. The bond wires may extend through a plurality of windows in the interposer. First and second dies may be attached to a first side of an interposer and may be electrically connected to a second side of the interposer through windows and third and fourth dies may be attached to a second side of the interposer and may be electrically connected to the first side of the interposer through windows.

Abstract: Disclosed are an array substrate and a display device. The array substrate comprises a plurality of first data lines (1) parallel to a short side of the array substrate, a plurality of second data lines (2) parallel to a long side of the array substrate, a first integrated circuit (3) arranged in a short-side frame. The plurality of the second data lines (2) are configured for connecting the first integrated circuit (3) with the plurality of the first data lines (1), and the first integrated circuit (3) transmits data signal to the plurality of first data lines (1) through the plurality of second data lines (2). The first integrated circuit for transmitting signals to the data lines is arranged in the short-side frame, so that there is no more integrated circuit arranged in the long-side frame, thereby reducing the border-width of the long-side frame and increasing the visual effect for the viewer.

Abstract: An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate includes: a base substrate; a plurality of gate lines and a plurality of data lines disposed on the base substrate and configured to define a plurality of pixel regions; pixel electrodes and common electrodes disposed in each pixel region and arranged in different layers; and shielding electrodes being at least formed in regions corresponding to the data lines on the base substrate, being arranged in different layers from the common electrodes, and being not electrically connected with the pixel electrodes and the common electrodes.

Abstract: Semiconductor device packages for incorporation into semiconductor device assemblies may include a substrate including an array of electrically conductive elements located on a lower surface of the substrate. A window may extend through the substrate from the lower surface to an upper surface of the substrate. The array of electrically conductive elements may at least partially laterally surround a periphery of the window, and the substrate may extend laterally beyond the array of electrically conductive elements. Semiconductor devices may be supported on the upper surface of the substrate around a periphery of the array of electrically conductive elements. The semiconductor devices may be electrically connected to at least some of the electrically conductive elements of the array by routing elements extending from the semiconductor devices toward the window.

Abstract: The invention provides an array substrate and a manufacturing method thereof. The array substrate comprises a substrate body, a common electrode, a light shield layer, an insulating layer, a polycrystalline silicon layer, a gate insulating layer, a gate electrode, a medium layer and a source-drain electrode. The array substrate is characterized in that the common electrode is formed on the substrate body, the light shield layer is positioned on the common electrode, the insulating layer is positioned on the light shield layer and the common electrode, and the gate electrode is connected with the common electrode through a through hole.

Abstract: The invention provides a luminescent material (10) comprising quantum dots (100), wherein the luminescent material (10) further comprises a capping agent (110) coordinating to the quantum dots (10), wherein the capping agent comprises MxOy(OH)zn, wherein M is selected from the group consisting of B, Al, P, S, V, Zn, Ga, Ge, As, Se, Nb, Mo, Cd, In, Sn, Sb, Te, Ta and W, wherein x?1, y+z?1, and wherein n indicates a positive or negative charge of the capping agent.

Abstract: Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication.

Abstract: Disclosed are a light emitting device, a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer comprising a barrier layer which is disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and which has an un-doped area and a doped area with dopants.

Abstract: A sensor (2) is arranged at a main surface (10) of a semiconductor substrate (1), and a filter (3) is arranged above the sensor. A through-substrate via (4) penetrates the substrate outside the region of the sensor. A semiconductor body is applied above the main surface and then partially removed at least in an area above the sensor. A portion of the semiconductor body remains above the through-substrate via as a frame layer (5). The filter is on a level with the frame layer.