Abstract: A CNFET based pulse generator, including a first Carbon Nanotube Field Effect Transistor (CNFET), a second CNFET, a third CNFET, a fourth CNFET, a fifth CNFET, a sixth CNFET, a seventh CNFET, an eighth CNFET, a ninth CNFET, a tenth CNFET, an eleventh CNFET, a twelfth CNFET, a thirteenth CNFET, and a fourteenth CNFET. The first CNFET, the third CNFET, the fifth CNFET, the seventh CNFET, the tenth CNFET, the twelfth CNFET, and the thirteenth CNFET are P-type CNFETs. The second CNFET, the fourth CNFET, the sixth CNFET, the eighth CNFET, the ninth CNFET, the eleventh CNFET, and the fourteenth CNFET are N-type CNFETs.

Abstract: A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric.

Abstract: A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.

Abstract: A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.

Abstract: Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.

Abstract: Provided are a mask assembly, an apparatus for manufacturing a display apparatus, and a method of manufacturing the display apparatus. The mask assembly includes a mask comprising an opening having a pattern; and a self-assembled monolayer (SAM) that is coated on at least a portion of the mask.

Abstract: A single fin or a pair of co-integrated n- and p- type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

Abstract: A thickness of material may be detached from a substrate along a cleave plane, utilizing a cleaving process controlled by a releasable constraint plate. In some embodiments this constraint plate may comprise a plate that can couple side forces (the “P-plate”) and a thin, softer compliant layer (the “S-layer”) situated between the P-plate and the substrate. In certain embodiments a porous surface within the releasable constraint plate and in contact to the substrate, allows the constraint plate to be secured to the substrate via a first pressure differential. Application of a combination of a second pressure differential within a pre-existing cleaved portion, and a linear force to a side of the releasable constraint plate bound to the substrate, generates loading that results in controlled cleaving along the cleave plane.

Abstract: A method of manufacturing an organic light emitting display panel, the method including: providing a pixel defined by an intersection of one of a plurality of data lines and one of a plurality of gate lines, the providing the pixel including: providing a transistor, providing a storage capacitor including: a first electrode, and a second electrode, and providing a semiconductor layer, providing a first plate partially overlapping the semiconductor layer in the pixel, the providing a first plate including: providing a gate portion of the transistor, and providing a capacitor-forming portion including the first electrode of the storage capacitor, and providing a second plate on the first plate in the pixel, the second plate including the second electrode of the storage capacitor, the second plate not overlapping the semiconductor layer.

Abstract: A semiconductor device, in which, in a density distribution of first conductivity type impurities in the first conductivity type region measured along a thickness direction of the semiconductor substrate, a local maximum value N1, a local minimum value N2, a local maximum value N3, and a density N4 are formed in this order from front surface side, a relationship of N1>N3>N2>N4 is satisfied, a relationship of N3/10>N2 is satisfied, and a distance “a” from the surface to the depth having the local maximum value N1 is larger than twice a distance “b” from the depth having the local maximum value N1 to the depth having the local minimum N2.

Abstract: The present invention is directed to a memory device including a first layer of memory cells with each cell of the first layer of memory cells including a two-terminal selection element coupled to a memory element in series; a plurality of first local wiring lines connected to one ends of the first layer of memory cells along a first direction with each of the first local wiring lines being electrically connected to two first line selection transistors at two ends thereof; and a plurality of second local wiring lines connected to other ends of the first layer of memory cells along a second direction substantially orthogonal to the first direction with each of the second local wiring lines being electrically connected to two second line selection transistors at two ends thereof.

Abstract: A method includes forming a set of fins composed of a first semiconductor material. The method further heats the set of fins to condense the fins and cause growth of a layer of oxide on vertical sidewalls thereof, masking a first sub-set of the fins, forming a plurality of voids in the oxide by removing a second sub-set of fins, where each void has a three-dimensional shape and dimensions that correspond to a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set, and epitaxially growing in the voids a third sub-set of fins. The third sub-set of fins is composed of a second semiconductor material that differs from the first semiconductor material. Each fin of the third subset has a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set. At least one structure formed by the method is also disclosed.

Abstract: A system and method for applying a fluid to a surface. The method includes the steps of: providing a deposition system; discharging fluid from the deposition system at a first, non-zero rate; detecting movement of the deposition system in proximity to a surface; and discharging fluid at a second rate while the deposition system is moving in proximity to the surface. The system comprises: a MEMS element coupled to a fluid reservoir and adapted to dispense fluid at a plurality of non-zero rates; at least one sensor; and a controller in communication with the MEMS element and at least one sensor and adapted to receive an output from the sensor and to alter the deposition rate of the MEMS element according to the sensor output.

Abstract: There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. A light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air. Therefore, a light-emitting element with high reliability and long lifetime and a display device using the light-emitting element can be provided.

Abstract: An organic electroluminescent device and a manufacturing method thereof, and a display device. The organic electroluminescent device comprises comprising a base substrate, a packaging structure, an organic electroluminescent structure located between the base substrate and the packaging structure, and a flexible printed circuit board; the base substrate being provided with a peripheral wiring structure electrically connected with an internal wiring of the organic electroluminescent structure; the peripheral wiring structure including a welding part. The welding part has a first surface facing the base substrate, at least a portion of the first surface being exposed to electrically connect with a welding terminal of the flexible printed circuit board.

Abstract: A method of patterning a silicon containing ARC (anti-reflective coating) layer underlying a patterned layer is described that includes establishing a flow of a process gas to a plasma processing system, selecting a process condition that increases an etch selectivity of the silicon containing ARC layer relative to the patterned layer, igniting plasma from the process gas using a plasma source in accordance with the process condition, and exposing the substrate to the plasma to extend the feature pattern of the patterned layer into the silicon containing ARC layer. The composition of the process gas and the flow rate(s) of the gaseous constituents in the process gas are selected to adjust the carbon-fluorine content.

Abstract: A system and method for dispensing a fluid within an environment. The method includes the steps of: providing a dispensing system within an environment; discharging fluid from the dispensing system at a first, non-zero rate; detecting a change in the environment; and discharging fluid at a second rate after detecting the environmental change. The system comprises: a MEMS element coupled to a fluid reservoir and adapted to dispense fluid at a plurality of non-zero rates; at least one sensor; and a controller in communication with the MEMS element and at least one sensor and adapted to receive an output from the sensor and to alter the dispensing rate of the MEMS element according to the sensor output.

Abstract: Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure.

Abstract: A device comprises a semiconductor substrate having first and second implant regions and an electrode above and between the first and second implant regions of a first dopant type. A contact structure is in direct contact with the first and second implant regions and the electrode. A third implant region has a second dopant type different from the first dopant type. A bulk contact is provided on the third implant.

Abstract: A grid for minimizing effects of ion divergence in plasma ion implant. The plasma grid is made of a flat plate having a plurality of holes, wherein the holes are arranged in a plurality of rows and a plurality of columns thereby forming beamlets of ions that diverge in one direction. A mask is used to form the implanted shapes on the wafer, wherein the holes in the mask are oriented orthogonally to the direction of beamlet divergence.