Abstract: A method for making moisture resistant semiconductor devices having organic substrates targets each of the potentially critical interfaces within a semiconductor device having the potential for delamination and cracking. An organic substrate (110) is designed to include a solid pad (116) having a chemically created oxide layer (118) formed thereon. A silicone-based die attach material (108) is dispensed and gelled very soon after dispensing to prevent excessive bleed. A semiconductor die (102) is mounted to the substrate after undergoing a cleaning operation to remove contaminants from the backside of the die. Prior to molding compound encapsulation and subsequent to die attach material cure, the substrate is cleaned to improve adhesion to the die attach material fillet (122).

Abstract: A compliant contact system for making a temporary electrical connection with a semiconductor die for testing and a method for fabricating the compliant contact system are provided. The compliant contact system is adapted for use with a test apparatus for known good die. The compliant contact system includes an interconnect, and can include an alignment fixture for aligning the die with the interconnect. The interconnect includes a pattern of compliant contacts adapted to contact the bond pads on the die. The compliant contacts are formed as metal traces on a silicon substrate. The end portions of the metal traces are cantilevered over a pit etched into the substrate, and are adapted to flex to compensate for dimensional variations in the bond pads and to provide a bias force against the bond pads.

Abstract: In a lead frame, leads are formed on a surface of protective insulation film having a device hole. Protruding electrodes (solder balls) are formed on the surface of the leads opposite the surface closer to the protective insulation film. A reinforcement plate is also formed on the rear surface of the protective insulation film.

Abstract: A method of making a semiconductor package and the package comprising the steps of providing a base having a plurality of cavities therein, forming a plurality of sets of spaced apart first apertures extending entirely through the base, each of the sets of spaced apart first apertures surrounding one of the cavities, forming a plurality of sets of second apertures extending partially through the base, each of the second apertures of a set being interconnected with a pair of adjacent ones of the first apertures from one of the sets to form a continuous groove extending partially through the base and surrounding one of the cavities and then causing the second apertures to extend entirely through the base to form individual packages associated with each of the cavities. The base is a cast base and the first and second apertures are preferably cast into said base.

Abstract: A method of continuous manufacture of semiconductor integrated circuits, said method and apparatus adapted to contain the semiconductor substrate, semiconductor deposition coating processes, and etching processes within a substantially collocated series of process chambers so that the semiconductor travels from one chamber to the next without exposure to airborne impurities and contact with manufacturing personnel. The invention has particular utility in the high volume fabrication of large surface area semiconductor circuits such as active matrix liquid crystal displays. The present invention contains a roll-to-roll and continuous belt embodiment.

Abstract: A method for manufacturing semiconductor chip package comprising steps of: (a) preparing a lead frame which comprises a pair of opposing side rails which have a plurality of through holes on their upper surface; a die pad onto which a chip will be mounted; a pair of rows of leads, each row being disposed at both sides of the die pad at a distance; and tiebars for mechanically and integrally connecting said die pad to said side rails; (b) filling a resin compound between leads and curing the resin compound to make dambars; (c) attaching said chip to an upper surface of said die pad, and electrically connecting said chip to leads; (d) encapsulating said chip, said die pad, said dambars, a part of said leads and a part of said tiebars to give a package body which is still attached to said lead frame; and (e) cutting said tiebars from lead frame to separate an individual package; and (f) forming leads extending from the package to have an appropriate bend shape is provided.

Abstract: A first electrode and a first insulating layer of electrode insulation are formed on a first semiconductor substrate. A second electrode and a second insulating layer of electrode insulation are formed on a second semiconductor substrate. The first semiconductor substrate has at its surface a pattern of recesses/projections (i.e., a pattern of sawteeth in cross section) at regular intervals in stripe arrangement. Likewise, the second semiconductor substrate has at its surface a pattern of recesses/projections (i.e., a pattern of sawteeth in cross section) at regular intervals in stripe arrangement, wherein the pattern of the second semiconductor substrate has a phase shift of 180 degrees with respect to the pattern of the first semiconductor substrate. The first and second semiconductor substrates are bonded together with their patterns in engagement.

Abstract: An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap.

Abstract: A leadframes is provided with at least one supporting portion extending from an island thereof in the direction opposite to a surface on which a semiconductor chip is mounted, so that the supporting portion comes into contact with a bottom surface of a cavity of a mold for encapsulation of semiconductor chips with a resin when said mold is closed.

Abstract: A leadframe integrated circuit package is provide with an interposer structure for electrically interconnecting a die with the leadframe. The interposer has a rigid substrate, which is mounted in the leadframe in place of a conventional integrated circuit die. Interposer bonding pads at the periphery of the substrate are connected to bond fingers of the leadframe, e.g., by wire bonding. The interposer bonding pads are electrically connected to the die using a network of routing lines connected to a central array of interposer array pads. The array of interposer array pads is connected to a corresponding array of die array pads on the die using metal bumps.

Abstract: A semiconductor device assembly having external connections, including power supply connections such as to a power source or ground, is made without resort to bond fingers. Rather, external connections are directly made from a semiconductor die to a conductive layer. The conductive layer is disposed on one surface of a printed wring board and is divided into electrically insulated conductive segments. Each of the conductive segments is connected to an external connection, and includes one or more interconnects that can be directly connected to a semiconductor die. The conductive segments are surrounded by an array of bond fingers which serve to connect the semiconductor die to further external connections, such as signal connections. The present invention is especially advantageous in the fabrication of pin grid array (PGA) and ball grid array (BGA) type integrated circuit packages.

Abstract: A method and apparatus for assembling a temporary package for a semiconductor die are provided. The temporary package includes a package base, an interconnect for establishing electrical communication with the die, and a force applying mechanism for biasing the die against the interconnect. The method includes the steps of: supporting the package base; aligning the die with the interconnect held in the package base; placing the die and interconnect in contact; and then attaching the force applying mechanism to the base while it is allowed to slide along a plane parallel to the base to compensate for misalignment. The apparatus includes a movable support for the package base; an optical probe for aligning the die and interconnect; a vacuum conduit for placing the die in contact with the interconnect; and a slide holder for attaching the force applying mechanism to the base.

Abstract: An LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. An underfill material is introduced between each lead finger and semiconductor die, extending from the bonding location of the die and the edge of the die, in order to prevent filler particles from lodging between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The seal created by the underfill material reduces point stresses on the active surface of the die usually caused by the filler particles. The decreased flexure in the leads further enhances the locking of the leads in position with respect to the die.

Abstract: There is provided a semiconductor device having a very thin, highly reliable semiconductor package and a method of easily manufacturing the semiconductor apparatus. The method comprises a first step of coating and melting a thermosetting resin in a mold for resin sealing, while keeping the mold at a predetermined temperature, the mold being divided into an upper mold and a lower mold, a second step of fixing within the mold a lead frame supporting a semiconductor chip, and a third step of applying a pressure on the mold and compression-molding the resin, thus forming a package.

Abstract: A groove is formed on a semiconductor substrate. A mask material layer is so formed on the surface of the semiconductor substrate as to open a groove region. With the mask material layer used as a mask, a semiconductor layer is selectively formed on the semiconductor substrate exposed with the inner wall surface of the groove. Then, the mask material layer is removed. An insulating film is formed on the semiconductor layer formed on the inner wall surface of the groove and the surface of the semiconductor substrate. The groove is buried with a conductor.

Abstract: This invention provides a method for manufacturing a semiconductor device having molded resin encapsulating a semiconductor chip and external leads extending from this molded resin to the outside, wherein excess resin projecting from edge portions of the molded resin is removed after a resin encapsulating step and a wax film is reformed on break surfaces and cracked parts of the molded resin produced in the excess resin removing step by heating the molded resin to a predetermined temperature after removing tie-bars from the external leads, whereby abnormal growth of solder between the external leads in a subsequent solder plating process is prevented and failures caused by short-circuiting between terminals are thereby prevented.

Abstract: An integrated circuit package of this invention includes a series of nonconductive rigid substrates, each substrate having a pattern of generally coplanar bond fingers embedded thereupon. An integrated circuit die is connected to individual bond fingers of varying bond finger patterns. Individual bond fingers are connected to package terminals by medial leads, which are generally perpendicular to the bond finger patterns. Semiconductor die packages having both top and bottom package terminals are thus produced. Methods and devices are shown.

Abstract: A semiconductor apparatus has a wiring board having a wiring pattern and a plurality of connection electrodes formed on a surface thereof with the connection electrodes being electrically connected to the wiring pattern. A semiconductor device is mounted on a main surface of the wiring board and electrically connected to the wiring pattern. A resin-sealed structure is formed by a transfer mold for coating the main surface of the wiring board and the semiconductor device and having sides with a predetermined taper angle after coating. Those side edge portions of the resin-sealed structure which contact the main surface of the wiring board are in contact with edge portions of respective sides of the wiring board.

Abstract: A method and apparatus for connecting a lead of a lead frame to a contact pad of a semiconductor chip using a laser or other energy beam is herein disclosed. The lead may be wire bonded to the contact pad by heating the ends of a wire until the wire fuses to the contact pad and lead or an energy-fusible, electrically-conductive material may be used to bond the ends of the wire to the contact pad and lead. In addition, this invention has utility for both conventional lead frame/semiconductor chip configurations and lead-over-chip configurations. In addition, with a lead-over-chip configuration, the lead may be directly bonded to the contact pad with a conductive material disposed between the lead and the contact pad.

Abstract: Disclosed is a die structure which allows some or all routing to be performed in an integrated circuit packaging substrate (e.g., a package or circuit board). The packaging substrate acts as one or more interconnect levels. The die and packaging substrate arrangement takes the form of a flip chip design in which multiple solder bumps are formed on an active surface of the die. The active surface is largely or fully "populated" with such solder bumps to allow electrical connection to the packaging substrate at many different sites, depending upon the specific design employed. The solder bumps are electrically connected to various device elements or circuit components on the die itself. In this manner, many different integrated circuit designs may be implemented with the die (in the manner of a gate array) by employing different routing arrangements in the packaging substrate and allowing contact with subsets of the solder pad array.