Abstract: An outer lead having a plurality of external leads 1 for electrically connecting the semiconductor IC of a semiconductor IC package to external devices comprises a base plate 11, a plated base structure formed over the surface of the base plate 11 and consisting of a plurality of plated base layers 12, 13 and 14 of Ni or a Ni alloy, and a surface layer 15 of Au or an Au alloy formed over the uppermost plated base layer 14 of the plated base structure. The number of the plated base layers is at least three. Each plated base layer 12, 13 and 14 of the plated base structure is subjected to crystal-growth annealing after being formed by plating to crystal-grow the grains thereof. A method of fabricating such an outer lead is provided.

Abstract: Integrated circuits utilizing piezoelectric elements can be advantageously constructed by bonding elements together via direct bonds. Such integrated circuits include an electro-acoustic hybrid integrated circuit such as a voltage controlled oscillator wherein a semiconductor substrate having an active element is bonded through direct bonding to a surface acoustic wave resonator or a quartz oscillator as an electro-acoustic element. A quartz device can also be provided which includes a quartz plate, excitation electrodes on opposite surfaces, and a holding member made of a material having a thermal expansion coefficient substantially equal to that of the quartz plate. The holding member is connected to the quartz plate by direct bonding without using any adhesives. Because the thermal expansion coefficients of the quartz plate and the holding member are equal, no thermal stress occurs in the bonding area.

Abstract: A flux is applied to a circuit board on which solder is deposited beforehand. Then, the circuit board is subjected to reflow and then to rinsing. After the rinsing, an IC chip 1 having metal bumps on its electrodes, is mounted to the circuit board. Before the mounting, the chip 1 and circuit board are heated in an inactive gas atmosphere having a low oxygen concentration. At the time of mounting, the solder is melted at a temperature higher than its melting point so as to connect the chip 1 to the circuit board.

Abstract: Solder interconnection encapsulant, encapsulated structure and method for its fabrication and use, whereby the gap created by solder connections between a carrier substrate and a semiconductor device is filled with a composition obtained from curing a preparation containing a cycloaliphatic polyepoxide and/or curable cyanate ester or prepolymer thereof; filler, e.g., an aluminum nitride or aluminum oxide filler, having a maximum particle size of 31 microns.

Abstract: According to this invention, an etching stopper film constituted by a silicon nitride film is stacked on an insulating film constituted by a silicon oxide film for protecting a wiring to prevent damage to the wiring caused by anisotropic dry etching for forming a contact hole. A resist pattern having the same shape as that of the contact hole is formed by using a reflection prevention film containing nitrogen atoms, the etching stopper film and the reflection prevention film in a contact hole formation region which contain nitrogen atoms and have equal selectivity ratios under a predetermined condition are simultaneously removed by etching, so that a semiconductor device having stable performance and simple manufacturing steps can be obtained.

Abstract: Photoimageable dielectric materials are coated on substrates, selectively exposed and developed, whereby small vias and interconnection openings are formed between adjacently spaced circuit layers. A conductive paste may be used to provide sequential layer interconnection and surface planarization. No adhesives are required in the manufacture of a circuit assembly having multiple circuit and dielectric layers, and the manufacturing method avoids the requirement for drilled through holes and blind vias.

Abstract: Disclosed is a method for fabricating a planar buried heterostructure laser diode, comprising the steps of sequentially forming a first clad layer, an undoped active layer and a second clad layer on a substrate so as to complete a first crystal growth; forming a patterned mask layer on the second clad layer; non-selectively etching the second clad layer, the active layer, the first clad layer and the substrate using the mask layer as an etching mask; selectively etching the substrate and the first and second layers; sequentially forming a first and second current blocking layers on a structure formed by the selective etching step so as to complete a second crystal growth; sequentially forming a third clad layer and an ohmic contact layer thereon after removal of the mask layer so as to complete a third crystal growth; and forming a first electrode on a rear surface of the substrate and forming a second electrode on a surface of the third clad layer.

Abstract: A method for forming an electrical connection between a semiconductor die and a corresponding electrical component mounted within an electrical device is provided. The method includes wire bonding metal wires to the bond pads of the die and then severing the metal wires to form loose leads attached to the bond pads. With the die mounted to the electrical device, the loose leads are bonded to the electrical component using a bonding tip. In an illustrative embodiment, the electrical device is a field emission display package and the electrical component is conductive traces for the package. Advantageous, the method can be used to form the electrical connection between the die mounted in a sealed space and the corresponding electrical component which is outside of the sealed space.

Abstract: A semiconductor processing method of forming an electrically conductive interconnect line having an electrical conductive covering predominately coextensive therewith, includes, a) providing an conductive interconnect line over a first electrically insulating material, the line having a top and sidewalls; b) selectively depositing a second electrically insulating material layer over the interconnect line and the first insulating material in a manner which deposits a greater thickness of the second insulating material atop the interconnect line than a thickness of the second insulating material over the first insulating material; c) anisotropically etching the second insulating material layer inwardly to at least the first insulating material yet leaving second insulating material over the top and the sidewalls of the interconnect line; and d) providing an electrically conductive layer over the anisotropically etched second insulating layer to form a conductive layer which is predominately coextensive with the

Abstract: An integrated-circuit interconnect which can be formed at the wafer level is achieved by depositing an intentionally stressed contact layer over a release layer which is subsequently removed. The removal of the release layer permits a portion of the contact layer to curve away from the surface of an integrated circuit chip. The result is a spring contact having a base portion joined to a metal member of the chip and a spring portion which is available for joining to other metal members, e.g., on a substrate or another chip. The resilience of the spring portion can also be used to position and align integrated circuit elements.

Abstract: According to a face-down-mounting semiconductor device wherein electrode pads on a semiconductor chip and lead terminals are electrically connected to each other by plating bonding, and a method of manufacturing the semiconductor device, a guide tool is placed on the surface of a semiconductor chip. The guide tool includes guide holes corresponding in position to electrode pads. Columnar lead terminals are inserted into the guide holes of the guide tool. In this state, the semiconductor chip is soaked in a plating solution, together with the guide tool, to execute plating bonding. Since, therefore, the lead terminals can be brought into reliable contact with the electrode pads, metal plating layers can be grown sufficiently between them, thereby improving in reliability of melting bonding.

Abstract: The invention is to an array of stacked devices utilizing vertical surface mounted semiconductor devices stacked side by side and inserting the stack of devices into a casing. The packaged stack of devices creates a cube package which is capable of replacing SIMM boards, and saves considerable space. The casing dissipates heat generated in the devices, and may be of metal or thermally conductive plastic.

Abstract: Ceramic semiconductor packages which comprise a lead frame (1) having registering holes (4, 5) and a ceramic substrate (2) having a thermally fusible bonding material such as a resin or glass applied to the sealing surface (6) of the substrate are manufactured by positioning the lead frame, using a transfer device (14), on a lead frame-supporting plate (11) having holes (20, 21), through which positioning pins (22) formed on a positioning base (12) are made to protrude by lifting the base (12) by a driving mechanism (13), in such a manner that the positioning pins pass through the registering holes (4, 5) of the lead frame. The substrate is then centered and positioned on the lead frame using a transfer device (15) having chuck hands (33). Thereafter, the bonding material is fused by heating in a heating furnace (16) to bond the lead frame and the substrate.

Abstract: Bond pads (394, 106) and bond pad openings (62, 108) are formed such that the bond pad openings (62, 108) are asymmetric to the conductive sections (398, 106) of the bond pads (394, 106). If the bond pads are more likely to lift from the scribe line side of the bond pad (394, 106), the bond pad openings (62, 108) are formed such that the passivation layer (52) overlies more of the conductive section (398, 106) near the scribe line (40). If the bond pads (394, 106) are more likely to lift from the other side, the passivation layer (52) overlies more of the other side of the conductive section (398, 106). In addition to reducing the risk of lifting, contamination problems should also be reduced.

Abstract: A semiconductor chip package and method of making same wherein the package comprises a ceramic substrate having two layers of thermally and electrically conductive material (e.g., copper) on opposing surfaces thereof, these layers thermally and electrically coupled by metal material located within holes provided in the ceramic. A semiconductor chip is mounted on one of these layers and the contact sites thereof electrically coupled to spaced circuitry which, in a preferred embodiment, is formed simultaneously with both thermally conductive layers. Coupling of the circuitry to an external substrate (e.g., printed circuit board) is preferably accomplished using metallic spring clips. These clips are preferably soldered in position. A preferred metal for being positioned within the hole(s) is solder, one example being 10:90 tin:lead solder.

Abstract: An integrated circuit package includes an integrated circuit chip, a substrate which holds the chip, and a heat conduction mechanism which provides a path for conducting heat from the chip to a fluid medium; wherein the heat conduction mechanism is characterized as having a pressed joint which is comprised of: 1) a member that is made primarily of aluminum or copper, having a solid polysiloxane coating of less than 200.ANG. thickness, and 2) a liquid metal alloy in contact with the coating. This solid coating, on the aluminum or copper member, is fabricated without any expensive equipment by the steps of: 1) forming a liquid coating of a polysiloxane solution on the aluminum or copper member; and 2) baking that member with its liquid coating at temperatures of 100.degree. C.-300.degree. C. for 0.5 hours-3.0 hours. Thereafter the integrated circuit package is completed by placing the member with its solid coat in the heat conducting path such that a liquid metal alloy is in contact with the solid coat.

Abstract: The present invention is a method for fabricating interconnecting lines and contacts using conformal deposition. This invention applies patterning trenches simultaneously for interconnecting lines and contact holes and forming spacers technologies to make fully filled interconnecting line and contact holes. Then, utilizing the conformal deposition and blanket etch-back etching method, the present invention can fabricating interconnecting lines and contacts simultaneously.

Abstract: A method of packaging a semiconductor device includes providing a chase (11) with a cavity (12). The cavity (12) has a cavity sidewall (13). A substrate (19) is provided having a substrate sidewall (20) wherein the substrate (19) is positioned in the cavity (12). A space or gap (21) is formed between the substrate sidewall (20) and the cavity sidewall (13). To insulate the gap (21) from mold compound (27), a barrier layer (22) is placed adjacent to the chase (11) and adjacent to the substrate (19) wherein the barrier layer (22) overlays a portion of the space or gap (21). Mold compound (27) is injected over the barrier layer (22), over the portion of the space or gap (21), and toward the substrate (19). The barrier layer (22) is used to prohibit the mold compound (27) from contacting the substrate sidewall (20) and the cavity sidewall (13) when the substrate (19) is being encapsulated.

Abstract: A method for attaching a semiconductor wafer section to a lead free comprises a carrier having an outside surface and an adhesive coating the carrier. Prior to use, the structure can be placed onto spools for easy shipment and storage.

Abstract: An integrated circuit probing method and apparatus therefor. The apparatus includes a main system controller coupled to a network interface, graphic user interface, and equipment interface. A high speed bus connects the main system controller to a group of subsystems. The subsystems includes subsystems such as input cassettes, input frame handing, frame to align, die align, die probing, die bin and die output, output cassettes subsystem, among others. The integrated circuit probing apparatus allows for probing of each individual die through the die probing subsystem, typically a high speed subsystem.