Abstract: There is provided a mounting construction which prevents leads of a semiconductor device from being short circuited when the semiconductor device is mounted on a mounting board so that mountability of the semiconductor device is improved. A plurality of outer leads extend from sides of a package of the semiconductor device. A mounting board has a surface on which a plurality of terminals to be electrically connected to the semiconductor device are provided. A mounting member is mounted on the mounting board separately from the semiconductor device. The semiconductor device is attached to the mounting member. The mounting member has a frame member forming a space in which the semiconductor device is placed. A first connecting lead has a first lead connecting portion and a first external connecting portion to be connected to a one of terminals provided on the mounting board. The first external connecting portion extends along a bottom surface of the frame member.

Abstract: A semiconductor package lead deflash method comprises the steps of forming a plating thin film on a plurality of leads, weakening an adhesive force of the plating thin film, and removing a flash and the plating thin film formed therebeneath respectively from the plurality of leads. The lead deflash method enables complete elimination of the lead flash formed during a package fabrication, and additionally serves as a pollution deterrent by adopting a chemical-free deflash method.

Abstract: A semiconductor integrated circuit (IC) die is made with enhanced resilience to handling, testing, and storage, associated with its qualification and distribution as a KNOWN GOOD DIE (KGD). The IC device has a mechanically tough and chemically inert top layer to protect it from damage. The device contacts are made of thin film metals which facilitate reversible electrical connections used in KGD testing. The overall contact structure protects the device from irreversible damage during the connection, test, and disconnection sequence.

Abstract: Methods of forming two-sided high density multilayer interconnect (HDMI) structures on a relatively large carrier and subsequently releasing and removing one or more structures to provide useable flexible interconnects or decals. In general, a carrier is provided and a release layer is formed on the carrier. Flexible high density multilayer interconnect structures are fabricated on the release layer. The release layer is processed to release and remove one or more flexible HDMI structures from the carrier. The carrier may be an ultraviolet transparent substrate, such as quartz, for example, and the release layer may be a polyimide layer. The HDMI structures are released by irradiating the release layer through the transparent carrier using ultraviolet radiation from an ultraviolet radiation source. Alternatively, a silicon carrier may be used that has a metal or silicon dioxide release layer formed thereon.

Abstract: A method is provided for forming a bolometer having an infrared sensitive material disposed on a platform elevated over a surface of a semiconductor body. The method includes forming a thermally insulating support layer to provide the platform and legs for supporting the platform over the semiconductor body. A layer of electrically conductive material is formed over the support layer and onto electrical contacts of an electronic circuit formed in the semiconductor body. The layer of electrically conductive material is patterned into electrical conductors passing, at a proximal end thereof, from the contact region of the electronic circuit upwardly to, at the distal end thereof, the platform region. The patterned electrically conductive layer is used as a mask for selectively removing portions of the support layer exposed by the patterned electrically conductive layer while portions of the support layer remain disposed under such patterned electrically layer.

Abstract: A highly reliable semiconductor device and a method of manufacturing the same. The semiconductor device is constituted by a semiconductor element which is disposed within a space portion defined by leads of a lead frame or fixed to a die pad of a lead frame and which has bonding pads connected to the leads through wires respectively, and a heat radiation block/plate which is made of a good thermally conductive material and which has an outer periphery having a size sufficiently to overlap the leads so that the heat radiation block/plate is disposed on the leads partly through a tape-like insulator, the semiconductor element being disposed on a center portion of the heat radiation block/plate directly or through the die pad. The semiconductor device is sealed with resin or the like with part of the leads and an end surface of the heat radiation block/plate left exposed or with part of the leads left exposed.

Abstract: A method of passivating organic devices positioned on a supporting transparent plastic substrate including the steps of overcoating the plastic substrate with a multi-layer overcoating, composed of alternating layers of a transparent polymer film and a transparent dielectric material, forming an organic device on the overcoated transparent plastic substrate and sealing the organic device formed on the overcoated plastic substrate. The polymer film layer used in overcoating the plastic substrate acts as a means of improving the barrier properties of the multi-layer overcoating and the dielectric material acts as a physical barrier to atmospheric elements which can corrode the organic device and are a detriment to the reliability of organic LEDs.

Abstract: An electrode terminal (5) provided on a surface of a semiconductor chip (4) has a square shape in plane view. Further, the projecting apex portion (8a) of a bump (8) provided on the electrode terminal (5) orients to a corner portion (5a) of the electrode terminal (5). Hereupon, a gold ball (2a) formed by melting the lower end portion of a gold wire (2) supplied through a capillary (1) is joined to the electrode terminal (5), and then the capillary (1) is moved in the direction of a diagonal line of the square electrode (5). Thus, the main portion of the gold wire (2) is separated from the gold ball (2a) so that the bump (8) is formed.

Abstract: An insulating film has conductive layers on a first surface and conductive protrusions on a second surface. The conductive layers are connected to the conductive protrusions via through holes provided in the insulating film. A semiconductor chip having pads is adhered by an adhesive layer to the insulating film. Then, the conductive layers are locally pressured, so that the conductive layers are electrically connected to respective ones of the pads.

Abstract: A multichip semiconductor structure and fabrication method having connect assemblies with fuses which facilitate burn-in stressing and electrical testing of the structure are presented. The structure comprises a multichip stack having standard transfer wire outs to an edge surface thereof. At least some wire outs to the edge surface have fuses electrically series connected thereto such that should an excessive current source/sink arise during burn-in stressing, the corresponding fuse will open circuit. A conductive structure is also disclosed that facilitates the formation of final, operational metallization wiring on the edge surface of the multichip structure prior to burn-in stressing and testing. This conductive structure includes a first conductive level and a second conductive level. The first conductive level has isolated conductors with ends disposed in close proximity.

Abstract: A diamond matrix metallic mesh suppresses RF energy, and particularly side lobe energy, in a phased array antenna, while passing main beam energy. The metal mesh emulates the structure of the bond segments joining the carbon atoms in a diamond structure. The wire diamond lattice structure is placed above an array of radiating elements to absorb side lobe energy. The wire lattice structure is fabricated through use of complementary forms which compress a wire into a required unit shape. Many unit shaped wires are placed in a form which hold the wires in the proper position. Other unit shaped wires are rotated 90 degrees and attached in place to the held wires. Additional unit shaped wires are added to form the basic interlocking cube structure of the diamond lattice.

Abstract: A socketed integrated circuit packaging system, including a packaged integrated circuit and a socket therefor, is disclosed. The integrated circuit package includes a device circuit board to which a thermally conductive slug is mounted; the underside of the device circuit board has a plurality of lands arranged in an array. The integrated circuit chip is mounted to the slug, through a hole in the device circuit board, and is wire-bonded to the device circuit board and thus to the lands on the underside. The socket is a molded frame, having a hole therethrough to receive the conductive slug of the integrated circuit package; the socket may also have its own thermally conductive slug disposed within the hole of the frame. The socket has spring contact members at locations matching the location of the lands on the device circuit board. The integrated circuit package may be inserted into the socket frame, held there by a metal or molded clip.

Abstract: In the disclosed method of manufacturing semiconductor devices with a single-sided resin-sealed package structure, when resin is filled into between the chip and the substrate, the occurrence of variations in the finishing dimensions of the package or defects in the outward appearance of the package is prevented.

Abstract: A method for interconnecting at least one semiconductor chip (14 or 36) having chip pads (16 or 38) includes applying a removable polymer layer (22 or 44) over the chip; forming vias (26 or 50) in the polymer layer aligned with predetermined chip pads; depositing a pattern of electrical conductors (28 or 52) over the polymer layer and into the vias; and removing the polymer layer. Prior to applying the polymer layer, the chip can be attached to a substrate by attaching a backside of the chip in a substrate chip well using a high temperature chip attach material (12) or by inserting the chip in a through hole of the substrate and applying a metallization plane (54) supporting the backside of the chip and at least a portion of the substrate.

Abstract: In a method of producing a resin-encapsulated semiconductor device, a lead frame having an semiconductor element bonded thereto and wire-bonded thereto is set as an insert into an injection mold. An epoxy resin molding compound is injected into the mold by an injection molding. In this method, an injection pressure of the injection molding machine is gradually increased in such a manner that a maximum pressure of 30 kg/cm.sup.2 to 300 kg/cm.sup.2 is achieved at the time when 80% to 95% of a total amount of the epoxy resin molding compound to be injected is injected into the mold. Subsequently, the remaining epoxy resin molding compound is injected into the mold at an injection pressure of 20 kg/cm.sup.2 to 100 kg/cm.sup.2. A heating cylinder of the injection molding machine is divided into a plurality of zones which are controlled in the temperature independently. The zone nearest to a nozzle of the heating cylinder is controlled to 65.degree. C.-110.degree. C.

Abstract: A flip-chip assembly and method for reducing the stress in its metal interconnections resulting from thermal mismatch includes a detector that has a radiation sensitive circuit on a substrate that is flip-chip connected to a layer of semiconductor material that is provided with a readout circuit. The substrate has a thermal coefficient of expansion (TCE) greater than the semiconductor layer such that operating the detector over a predetermined temperature range would stress the flip-chip connections. A first compensation layer on the readout chip has a TCE greater than the substrate's, and a second compensation layer on the first layer has a TCE approximately equal to the semiconductor layer's. The materials and thicknesses of the compensation layers are selected such that the TCE of a composite structure that includes the semiconductor and compensation layers is approximately equal to the substrate's TCE to avoid the stress over the predetermined temperature range.

Abstract: A solder bump is stenciled onto a substrate, providing bumped substrate at pitches below 400 microns. The solder is applied through stencil/mask and paste method; the mask, however, remains attached to the substrate during reflow. Pitches of greater than 400 microns may also be obtained through the invention. The invention further provides for generation of uniform, controllable volume metal balls.

Abstract: A method of forming an FET transistor comprises forming a stack of a gate oxide layer and a control gate electrode on a surface of a doped semiconductor substrate with counterdoped source/drain regions therein. A silicon oxide layer is formed over the stack of the gate oxide layer and the control gate electrode and exposed portions of the semiconductor substrate including the source/drain regions. Then the silicon oxide layer and the corners of the gate oxide layer are fluorinated by rapid thermal processing providing a fluorinated silicon oxide layer. The rapid thermal processing is performed in an atmosphere of NF.sub.3 gas and O.sub.2 gas at a temperature from about 900.degree. C. to about 1050.degree. C. for a time duration from about 10 seconds to about 50 seconds, and the fluorinated silicon oxide layer has a thickness from about 200 .ANG. to about 400 .ANG..

Abstract: An outer coating of an electrically conductive material having low wetability with respect to solder is deposited over a gold coating previously deposited on an electrical contact element. After soldering the contact element to a substrate, the portion of the outer coating not covered by solder is removed from the contact element. The method of joining a contact element to a substrate in accordance with the present invention effectively solves the problem of solder climb to the critical contact area of the element without the need to provide masking or apply plating resist coatings to selected areas of the element.

Abstract: Various improvements in the fabrication of an antifuse having silicon-amorphous silicon-metal layer structure are presented. Included are improved deposition techniques for the amorphous silicon layer. The improvements include steps for the fabrication of such an antifuse without the use of platinum and the resulting antifuse and contact structures.