Patents Examined by Kevin Verbrugge
  • Patent number: 10387066
    Abstract: In response to a cache flush event indicating that host data accumulated in a cache of a storage processor of a data storage system is to be flushed to a lower deck file system, an aggregation set of blocks is formed within the cache, and a digest calculation group is selected from within the aggregation set. Hardware vector processing logic is caused to simultaneously calculate crypto-digests from the blocks in the digest calculation group. If one of the resulting crypto-digests matches a previously generated crypto-digest, deduplication is performed that i) causes the lower deck file system to indicate the block of data from which the previously generated crypto-digest was generated and ii) discards the block that corresponds to the matching crypto-digest. Objects required by a digest generation component may be allocated in a just in time manner to avoid having to manage a pool of pre-allocated objects.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: August 20, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Istvan Gonczi, Ivan Bassov, Philippe Armangau
  • Patent number: 10387334
    Abstract: A circuit, for managing operations for accessing a flash memory on the basis of requests received from a main CPU and from an auxiliary CPU, may be configured to: associate with the main CPU, a higher access priority to the flash memory than the access priority of the auxiliary CPU; command, in the absence of further requests for accessing the flash memory, the access to the flash memory for the main or auxiliary CPU which has initiated a first access request; verify, following a receipt of a second access request, the access priority associated with this second access request; suspend one of the first or the second access request having lower priority; and authorize the other of the first or the second access request having higher priority.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 20, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Fabio Enrico Carlo Disegni, Federico Goller, Michele Febbrarino
  • Patent number: 10372681
    Abstract: A method and system for improving tape drive memory storage is provided. The method includes receiving, by a storage tape drive, a data stream for storage. The data stream is passed through a non-volatile memory device (NVS2) of the storage tape drive. The data stream is divided into adjacent variable length data chunks and a chunk list file including similarity identifiers for each of the adjacent variable length data chunks is generated and stored within a (non-volatile memory device) NVS1. Duplicate data including duplicated data with respect to a group of data chunks of the adjacent variable length data chunks is identified and deleted from the NVS2 of the storage tape drive such that the group of data chunks remains within NVS2. The group of data chunks is written to a data storage tape cartridge. Pointers identifying each data chunk and an associated storage position are generated and stored.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ole Asmussen, Robert Beiderbeck, Erik Rueger, Markus Schäfer
  • Patent number: 10372602
    Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: August 6, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Sanketh Nalli, Haris Volos, Kimberly Keeton
  • Patent number: 10366008
    Abstract: A data processing system includes a processor and a cache controller coupled to the processor, and adapted to be coupled to a memory. The cache controller uses the memory to form a pseudo direct mapped cache having a plurality of groups of pages. The memory forms a first number of selected pages, including a first page for storing a plurality of sets of tags and a plurality of remaining pages for storing data. Each tag, of the plurality of sets of tags, stores tags for respective entries in a corresponding one of the plurality of remaining pages.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: July 30, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Ganesh Balakrishnan, Vydhyanathan Kalyanasundharam, Kevin M. Lepak
  • Patent number: 10360155
    Abstract: The disclosure relates in some aspects to managing multi-tier memory, such as multi-tier NVM. Data that is originally written to a first tier (e.g., a fast tier) may be subsequently copied to a second tier (e.g., a slow tier). The data is temporarily left in the first tier until the space is needed for a subsequent write operation. Thus, for a period of time, a read operation is able to read the data from the first tier (e.g., the fast tier) instead of the second tier (e.g., the slow tier), thereby improving read performance. The disclosure relates in some aspects to a memory mapping scheme that enables a read operation to readily determine that data remains in the first tier and locate the data in that tier. Moreover, the scheme enables efficient reconfiguration of the mapping when the data in the first tier is erased.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: July 23, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Nicholas James Thomas, Matthew Davidson, Eran Erez
  • Patent number: 10359959
    Abstract: A solid state device is disclosed comprising an array of memory units, an interface connected to the memory units, at least one arrangement to monitor a temperature of the solid state device and an arrangement to monitor low power mode statistics of the solid state device and compare the low power mode statistics to a critical usage point power threshold at a temperature measured, wherein the arrangement to monitor the low power mode statistics of the solid state device is further configured to change a power mode of the solid state device based upon the low power mode statistics.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: July 23, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Avichay Haim Hodes, Alex Mostovoy, Judah Gamliel Hahn
  • Patent number: 10353623
    Abstract: According to an embodiment, a storage device includes an acquisition unit, a first generation unit, and an erase unit. The acquisition unit is configured to acquire erase permission notification which is generated based on specific data and first authentication information to authenticate the specific data, and includes a first erase code to erase the specific data and physical area information indicating a physical area of the specific data. The first generation unit is configured to generate a second erase code using the specific data stored in the physical area indicated by the physical area information and the first authentication information. The erase unit is configured to erase data stored in the physical area indicated by the physical area information when the first erase code corresponds to the second erase code.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: July 16, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Takahiro Yamaura, Tomonori Maegawa, Masataka Goto
  • Patent number: 10347284
    Abstract: An implementation of a system disclosed herein provides a method for managing data streams of sequential nature, wherein the method writes the sequential chunks (fragments) directly to an open band in the order these are received from the host and includes determining an end of the incoming data write request related to streaming data and in response to the determination of the end of the incoming data write request related to streaming data, copying remaining data from a current physical band mapped to logical block addresses LBAs related to the data write requests to the allocated (open) band.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: July 9, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Anil Kashyap, Brian T. Edgar
  • Patent number: 10346045
    Abstract: A method of managing a memory system is described, the memory system having a processor with a client interface, a buffer memory, and a storage memory. A LUN (logical unit) is exposed to the client, the LUN having a memory size, and QoS specification. When the processor receives a command from the client to write data to the LUN, determining if the QoS specification includes deduplication and: if the QoS does not include deduplication, processing the command by storing the data in the storage memory and creating metadata uniquely referencing a storage location of the data that is written; or if the QoS includes deduplication, determine if deduplication is possible while meeting a latency value as specified in the QoS specification and performing deduplication.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: July 9, 2019
    Assignee: VIOLIN SYSTEMS LLC
    Inventors: Amit Garg, Timothy Stoakes, Vikas Ratna
  • Patent number: 10338837
    Abstract: This disclosure relates to allocating memory resources of a computing device comprising non-volatile random access memory (NVRAM) and dynamic random access memory (DRAM). An exemplary method is performed for every independently executable component of an application and includes determining attributes of the component. The method also includes associating the component with a memory profile of a plurality of memory profiles based on the attributes, wherein each memory profile of the plurality of memory profiles specifies a number of banks of the NVRAM and a number of banks of the DRAM. The method also includes causing the computing device to generate an assignment of the component to banks of the NVRAM and DRAM based on the memory profile associated with the component so the computing device can execute the component using the banks of the NVRAM and DRAM based on the assignment.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: July 2, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Subrato Kumar De, Dexter Tamio Chun, Yanru Li, Bohuslav Rychlik, Richard Alan Stewart
  • Patent number: 10331555
    Abstract: Apparatus, systems, methods, and computer program products for dynamic memory compaction are disclosed. A memory device comprises a plurality of memory blocks and a controller for the memory device. A controller is configured to generate an input/output command to write a data chunk to a first memory block of a plurality of memory blocks. A controller is configured to compact an amount of valid data in a second memory block of a plurality of memory blocks based on a size of an I/O command.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: June 25, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ramanathan Muthiah, Ramkumar Ramamurthy, Balaji Thraksha Venkataramanan
  • Patent number: 10310761
    Abstract: A storage device includes a memory unit, an access monitor, and a memory configurator. The memory unit includes a plurality of memory blocks. The access monitor is configured to monitor whether an access mode of the memory unit is a continuous-access mode or a random-access mode, to generate a monitor signal. The memory configurator configures, according to the monitor signal, any of the memory blocks to be either in a cache mode or a SRAM state to generate a configuration signal.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: June 4, 2019
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Zongpu Qi, Di Hu, Wei Zhao, Zheng Wang, Xiaoyang Li
  • Patent number: 10303365
    Abstract: Fingerprints of data portions are distributed in a balanced manner across active controllers of a data storage system, and may be done so in such a manner that, when a new active controller is added to the system, fingerprint ownership and movement between pre-existing active controllers, and active controllers overall, is minimized When a new active controller is added to the system and fingerprints are redistributed, no fingerprint ownership may be re-assigned between pre-existing active controllers and no fingerprints may be moved between pre-existing active controllers, for example, between local memories of the active controller.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: May 28, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Peng Wu, Bin Dai, Rong Yu
  • Patent number: 10289557
    Abstract: A storage system and method for fast lookup in a table-caching database are provided. In one embodiment, a storage system is provided comprising a volatile memory, a non-volatile memory, and a controller. The controller is configured to store, in the volatile memory, a data structure representing a compressed version of a logical-to-physical address table stored in the non-volatile memory; and search the data structure for a physical address associated with a logical address, wherein the controller is configured to find any physical address in the data structure in a fixed amount of time. Other embodiments are provided.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yacov Duzly, Hadas Oshinsky
  • Patent number: 10282298
    Abstract: A system that uses a write-invalidate protocol has two types of stores: a traditional store that operates using a write-back policy that snoops for copies of the cache line at lower cache levels, and a store that writes, using a coherent write-through policy, directly to the last-level cache without snooping the lower cache levels. A separate store buffer may be maintained in the processor for the coherent write-through operations. A special bit may be maintained in the entries of a store buffer that is used for both traditional write-back policy stores and for coherent write-through policy. This bit indicates that loads and stores older than the last speculative store in the store buffer are allowed to be performed.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: May 7, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Patrick P. Lai
  • Patent number: 10282295
    Abstract: A method includes monitoring, at a cache coherence directory, states of cachelines stored in a cache hierarchy of a data processing system using a plurality of entries of the cache coherence directory. Each entry of the cache coherence directory is associated with a corresponding cache page of a plurality of cache pages, and each cache page representing a corresponding set of contiguous cachelines. The method further includes selectively evicting cachelines from a first cache of the cache hierarchy based on cacheline utilization densities of cache pages represented by the corresponding entries of the plurality of entries of the cache coherence directory.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: May 7, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William L. Walker, Michael W. Boyer, Yasuko Eckert, Gabriel H. Loh
  • Patent number: 10275173
    Abstract: A memory device includes an input/output interface, a bus of SPI type coupled to the input/output interface, and a plurality of individual non-volatile memory devices connected to the bus of SPI type. The chip select inputs of each individual memory device are all connected to one and the same chip select wire of the SPI bus. The individual memory devices are further configured and controllable so as to behave, as seen by the input/output interface, as a single non-volatile memory device, the total memory space of which has a total memory capacity equal to the sum of the individual memory capacities of the individual devices.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: April 30, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista
  • Patent number: 10261693
    Abstract: A storage system in one embodiment comprises a plurality of storage devices configured to store user data pages and metadata pages. Each of the user data pages has a logical address and a content-based signature derived from content of that data page, and each of the metadata pages characterizes a plurality of the user data pages and associates the content-based signatures of those user data pages with respective physical blocks in the storage devices. In conjunction with release of logical address space in the storage system, the released logical address space is made available to users in a first order based at least in part on released logical address, and multiple dereferencing operations are accumulated for respective ones of the physical blocks corresponding to the released logical address space. The accumulated dereferencing operations for the physical blocks are executed in a second order that differs from the first order.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 16, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Zvi Schneider, Anton Kucherov, Uri Shabi
  • Patent number: 10255206
    Abstract: Example implementations relate to a storage memory direct access (SMDA) provider. The SMDA provider may pin a storage memory region to a memory address of a consumer machine, the storage memory region corresponding to a storage range of a storage device requested by the consumer machine. The SMDA provider may atomically commit data in the storage memory region accessed by the consumer machine via the memory address.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: April 9, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Boris Zuckerman, Douglas L. Voigt, Suparna Bhattacharya