Abstract: A processing device in a memory system identifies a workload condition associated with a memory device. The processing device determines a host rate associated with the memory device based on the workload condition. The processing device detects a change in a condition of the memory device from a first state condition to a second state condition. The processing device determines, while the memory device is in the second state condition, an adjusted host rate, wherein the adjusted host rate is used to determine a credit consuming rate for a host operation.

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Abstract: A data processing method implemented by a network interface card device, wherein the method comprises receiving, from a first client, a first access request carrying an access address, detecting whether the first access request has a conflict; and processing the conflict according to a processing policy when the network interface card device detects that the first access request has a conflict.

Abstract: The present disclosure is directed to a reference voltage calibration. An apparatus includes a memory and a memory controller including a calibration circuit configured to perform a reference voltage calibration to determine a reference voltage used to distinguish between logic values read from the memory. The reference voltage calibration comprises performing horizontal calibrations at different reference voltage values to determine a range of delay values applied to a data strobe signal at which valid data is read from the memory. The calibration includes determining scores corresponding to ones of the plurality of horizontal calibrations in which a score for a particular one of the plurality of horizontal calibrations is based on a corresponding range of delay values and a reference voltage margin. Thereafter, the calibration circuit selects a calibrated reference voltage based on the scores corresponding to ones of the plurality of horizontal calibrations.

Abstract: The present disclosure relates to a storage device. The storage device includes a memory device including write-completed blocks storing data and free blocks each containing no data and a memory controller controlling the memory device to perform a garbage collection operation to store valid data stored in a victim block, among the write-completed blocks, in one of the free blocks based on the number of map segments including mapping information between logical addresses and physical addresses of the valid data, and erase counts of the free blocks.

Abstract: A system and method for a memory system are provided. A memory device includes an array of non-volatile memory cells. A memory controller is connected to the array of non-volatile memory cells. The memory controller is configured to perform the steps of receiving a request to read a value of a memory flag, wherein the memory flag includes a 2-bit value stored in a first memory cell and a second memory cell of the array of non-volatile memory cells, reading a first value of the first memory cell, reading a second value of the second memory cell, and determining the value of the memory flag based on the first value and the second value. In embodiments, the memory flag may have more than 2-bits.

Abstract: According to one embodiment, a storage device includes a first storage region assigned to a first user and a second storage region assigned to a second user. A first controller is capable of providing a data protection function to the first and second storage regions, and a second controller is capable of providing the data protection function to the second storage region. The first controller stores a table with information about the data protection function. The second controller can refer to the table. The first controller has a authority to execute a user authentication for the first storage region and the second storage region to determine whether the data protection function can be provided for the first or second storage regions.

Abstract: An apparatus controller includes a first communication module, a storage module, a data processing module, and a controller. The first communication module receives from each of one or more apparatuses, operation information indicating the operation state of the apparatus. The storage module stores the operation information in a cumulative manner. The data processing module combines, when values indicated by a plurality of operation information pieces successively received from the apparatus by the first communication module are equal to each other, the plurality of operation information pieces, thereby producing combined operation information. The controller causes, when the data processing module produces the combined operation information, the storage module to store the combined operation information instead of the plurality of operation information pieces.

Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to queue write commands received from a host. The commands may include a first write command to write first write data associated with a first stream and a second write command to write second write data associated with a second stream. When the first and second write commands are queued, the memory controller repeatedly performs a sequence of a first operation of acquiring a predetermined amount of the first write data from the host and then transmitting to the non-volatile memory, and a second operation of acquiring the predetermined amount of the second write data from the host and then transmitting to the non-volatile memory. The second operation in the sequence is started after completion of the first operation in the sequence.

Abstract: A memory system includes a nonvolatile memory including blocks, and a memory controller. The memory controller is configured to set each of the blocks to be in one of a plurality of states, including first, second, third, and fourth states. The memory controller is configured to detect a predetermined condition related to at least one of an amount of data being written into blocks in the first state and state transition of a block, upon detection of the predetermined condition, determine a maximum number of blocks to be in the fourth state based on a length of time during which each block in the fourth state has been in the fourth state, and perform an erase operation to cause one or more blocks in the third state to transition to the fourth state when a current number of blocks in the fourth state is less than the maximum number.

Abstract: A storage device can guarantee data write-requested from a host. The storage device includes: a buffer memory for storing data write-requested from the host; a memory device including user blocks, reserved blocks which substitute for the user blocks, and power loss protection blocks for storing buffer data stored in the buffer memory when a sudden power loss occurs, in which a power supply is abnormally interrupted; and a memory controller for determining whether any memory block capable of storing the write-requested data among the user blocks and the reserved blocks exists in response to a write operation error of the user blocks and the reserved blocks, and changing to a user block, one or more power loss protection blocks among the power loss protection blocks according to whether any memory block capable of storing the write-requested data exists.

Abstract: A storage controller and a storage system comprising the same are provided. Provided is a device security manager configured to set a first device security zone to allow a first tenant to access first tenant data stored in a non-volatile memory, receive access information from a host device and writing the received access information in a mapping table, wherein the access information includes a first host memory address in which the first tenant data is stored in the host device, a first namespace identifier for identifying the first tenant data stored in the non-volatile memory, a first logic block address corresponding to the first namespace identifier, and an encryption key, encrypt the first tenant data by using the encryption key, and write the encrypted first tenant data in the first device security zone of the non-volatile memory.

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums that allow a memory device to efficiently mark memory extents involved in an enhanced memory operation. An extent is marked if a meta state associated with the extent indicates that the extent is included in the enhanced memory operation. The largest memory extents of the operation are maintained in the memory device as a list of unmarked extents. When a primitive memory operation is received, the memory address is compared to the unmarked extents in the list to the meta state for that memory line. If the address is covered by the list of extents, or that line's meta state is marked, then the memory operation is performed including the enhanced memory operation.

Abstract: A storage device includes a nonvolatile memory device including a plurality of nonvolatile memories; a controller configured to allocate write blocks of the nonvolatile memory device to a plurality of streams provided from an outside; and a buffer memory configured to store a result of allocation of the write blocks to the plurality of streams, wherein the controller is further configured to reallocate the write blocks of the nonvolatile memory device to the plurality of streams based on the result of allocation stored in the buffer memory.

Abstract: Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

Abstract: A method of managing a memory system is described, the memory system having a processor with a client interface, a buffer memory, and a storage memory. A LUN (logical unit) is exposed to the client, the LUN having a memory size, and QoS specification. When the processor receives a command from the client to write data to the LUN, determining if the QoS specification includes deduplication and: if the QoS does not include deduplication, processing the command by storing the data in the storage memory and creating metadata uniquely referencing a storage location of the data that is written; or if the QoS includes deduplication, determine if deduplication is possible while meeting a latency value as specified in the QoS specification and performing deduplication.

Abstract: Devices and techniques for improving memory access operations of a memory device are provided. In an example, a method can include loading multiple LBA-to-physical address (L2P) regions of an L2P table from memory arrays of the memory device to a mapping cache in response to determining the LBA of the memory access command is not within the L2P region including of a mapping cache. When the memory access command is a sequential command, the multiple L2P regions loaded to the mapping cache can provide improved memory access performance.

Abstract: A circuit includes a data register configured to receive a signal including a plurality of data elements, a first selection circuit coupled to the data register, a counter, a second selection circuit coupled to the counter, and an inverter coupled between the counter and the second selection circuit. The data register outputs a plurality of bits of each data element to the first selection circuit, the counter and the inverter generate complementary signals in which sequential data elements have cyclical values that step in opposite directions, the second selection circuit alternatively outputs each of the complementary signals as a selection signal to the first selection circuit, and the first selection circuit, responsive to the selection signal, outputs the pluralities of bits of the data elements in alternating sequential orders.

Abstract: A system including a memory device and a processing device, the processing device to identify a first temperature level of a first set of memory blocks associated with the memory device, and a second temperature level of a second set of memory blocks associated with the memory device, and determine that a condition is satisfied based on a comparison of the first temperature level, the second temperature level, and an adjustable threshold level. In response to the condition being satisfied, the processing device is to combine the first set of memory blocks and the second set of memory blocks to generate a combined set of memory blocks.

Abstract: A storage system uses blocks of memory that are sized larger than a size of a zone. This means that the storage system stores multiple zones in a given block. Storing zones with different zone properties in a given block can be problematic, so the storage system obtains zone property information for each zone and stores zones with similar zone properties in a given block.