Abstract: A circuit includes a data register configured to receive and output successive data elements of a plurality of data elements responsive to a clock signal, wherein each data element of the plurality of data elements includes a total number of bits N. A signal generation portion is configured to output a first selection signal responsive to the clock signal, the first selection signal includes two alternating sequences, values of the first sequence increment from zero to N?1, and values of the second sequence decrement from N?1 to zero. A selection circuit coupled to the data register is configured to output the N bits of each data element of the plurality of data elements in a first sequential order responsive to the first sequence of the first selection signal, and in a second sequential order opposite the first sequential order responsive to the second sequence of the first selection signal.

Abstract: A method of managing a memory system is described, the memory system having a processor with a client interface, a buffer memory, and a storage memory. A LUN (logical unit) is exposed to the client, the LUN having a memory size, and QoS specification. When the processor receives a command from the client to write data to the LUN, determining if the QoS specification includes deduplication and: if the QoS does not include deduplication, processing the command by storing the data in the storage memory and creating metadata uniquely referencing a storage location of the data that is written; or if the QoS includes deduplication, determine if deduplication is possible while meeting a latency value as specified in the QoS specification and performing deduplication.

Abstract: A multi-tier memory comprises a block of memory with a plurality of sub-blocks (e.g., three sub-blocks). A garbage collection operation that chooses a source block based on a valid fragment count may not be suitable in multi-tier memories where sub-blocks have a dependency on one another (e.g., for an erase or program operation). The embodiments presented herein provide various garbage collection techniques that can be used in this situation. The techniques described herein can take in to account the valid fragment count of various sub-block groupings when deciding where to perform a garbage collection operation.

Abstract: A storage device includes a non-volatile memory device configured to store fast cell information obtained from a threshold voltage distribution formed through a one-shot program for memory cells; and a storage controller configured to read the fast cell information from the non-volatile memory device during booting or initialization to perform mapping a fast cell area based on a fast cell management policy, wherein the fast cell information is acquired through the one-shot program performed in a test stage or a mass production evaluation stage, and is stored in the non-volatile memory device before a firmware of the storage controller is executed.

Abstract: A system receives, via a graphical user interface (GUI), a user selection of one or more parameters indicative of a request to segment the memory device into partitions for use by a host system. Responsive to receiving, via the GUI, the user selection of the one or more parameters indicative of the request to segment the memory device into the partitions, the system configures a first partition of the partitions with one or more configuration settings based on the one or more parameters. To configure the first partition, the system determines a memory type from multiple memory types based on the one or more parameters, and configures the first partition of the partitions to operate as the determined memory type.

Abstract: A flash memory controller and a data reading method are provided. The flash memory controller includes a control logic circuit and a processor. The control logic circuit is coupled to a first chip-enable-signal controlled area of a flash memory through a channel to transmit data and commands. The processor controls the control logic circuit to transmit a first command and a second command to the first chip-enable-signal controlled area through the channel. The first command is configured to instruct the first chip-enable-signal controlled area to read stored data and read operating temperature information. In response to the transmission of the second command, the processor controls the control logic circuit to receive at least one of the stored data and the operating temperature information from the first chip-enable-signal controlled area.

Abstract: An apparatus includes a context identification circuit and a translation lookaside buffer (TLB) circuit. The context identification circuit may be configured to receive a context identifier assigned to a process being executed by a processor, and to assign a rename value to the context identifier that has fewer bits than the context identifier. The TLB circuit may be configured to receive a translation request for a virtual address that is associated with the process. The TLB circuit may be further configured to cache a translation of the virtual address to a corresponding physical address. The given entry may be tagged with a portion of the virtual address and the rename value. In response to a subsequent translation request for the virtual address, the TLB circuit may detect, using the portion of the virtual address and the rename value, a hit on the given entry of the TLB circuit.

Abstract: A storage device optimizes block closure in a memory device and maintains quality of service provided to a host device. The storage device receives commands from a host device and writes host data to a block in the memory device in a first state. When the storage device has not received a host write command for a host write idle time period, the storage device transitions to a second state, performs background operations at a first rate, and writes data to the block. When the storage device has not received a host read command or a host write command for a complete idle time period, the storage device transitions to a third state based, performs background operations at a second rate, and writes data to the block. The storage device uses the transitions between the states to maintain quality of service provided to the host device.

Abstract: Writing data in a storage system that includes a first type of storage device and a second type of storage device, including: selecting, for one or more unprocessed write requests, a target storage device type from the first type of storage device and the second type of storage device; issuing a first group of write requests to the first type of storage device, the first group of write requests addressed to one or more locations selected in dependence upon an expected address translation to be performed by the first type of storage device; and issuing a second group of write requests to the second type of storage device, the second group of write requests addressed to one or more locations selected in dependence upon a layout of memory in the second type of storage device.

Abstract: A data storage apparatus includes a nonvolatile memory device including a dump region configured to temporarily store data according to a state of applied power; and a controller configured to monitor health information of the dump region of the nonvolatile memory device, generate environmental information corresponding to a power loss protection (PLP) operation based on the health information, and share the environmental information with an external device.

Abstract: A data management apparatus, a data management method, and a data storage device are provided. The data management apparatus includes a management unit and a data migration unit. The management unit manages data transmission channels between two types of storage media with different transmission performance. Then, the data migration unit migrates data between the two types of storage media through the managed data transmission channels. In this way, the data management apparatus can directly migrate data between storage media with different transmission performance, and a CPU in a system does not need to perform processing such as instruction conversion and protocol conversion, so that a delay of performing the foregoing processing by the CPU can be shortened. In addition, because the CPU does not need to perform data migration, resource overheads of the CPU can be reduced.

Abstract: The application provides a method and a memory device for performing wear leveling in a memory device. The method includes: receiving data to be written transmitted by a host in the memory device; predicting the data to be written as a first type of data or a second type of data; referencing an erase count table in an erase count table buffer of the memory device; and when the data to be written is predicted as the first type of data, writing the data to be written into the block with a highest erase count among these blocks, and when the data to be written is predicted as the second type of data, writing the data to be written into the block with a lowest erase count among these blocks.

Abstract: Methods that may be performed by a universal flash storage (UFS) device of a computing device for configuring flash memory cells. Various embodiments may include setting a number of degraded triple-level cells (TLCs) attribute, and configuring at least one degraded TLC as at least one single-level cell (SLC) based on the number of degraded TLCs attribute, the at least one degraded TLC being not functional as a TLC and functional as an SLC. Some embodiments may include identifying the at least one degraded TLC based on at least one degradation attribute associated with the at least one degraded TLC, the at least one degradation attribute configured to indicate that the at least one degraded TLC is not functional as a TLC, and identifying an amount of degraded TLCs that are not functional as a TLC.

Abstract: A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.

Abstract: Methods and systems for existing software applications to automatically take advantage of multicore computer systems outside of the conventional simultaneous processing of multiple applications and without performance problems from cache misses and mismatched task processing times are presented. Unlike other multicore optimization techniques, the present invention uses techniques that are applied to design graphs and work for scaled and standard speedup-based parallel processing. The methods and systems optimize software designs that are attached to code for maximum performance on multicore computer hardware by analyzing and modifying loop structures to produce a general parallel solution, not just simple loop unrolling.

Abstract: Examples described herein relate to an apparatus comprising: circuitry to receive a request to store data as a part of a matrix in a memory device; circuitry to allocate address mappings to the data to reduce a number of sequential accesses to a same partition of a portion of the memory device; circuitry to store the address mappings for access with a read operation; and circuitry to cause storage of the data into the memory device according to the address mappings. In some examples, the matrix comprises one or more columns and/or one or more rows. In some examples, the memory device comprises one or more of: a three-dimensional (3D) cross point memory device, volatile memory device, or non-volatile memory device.

Abstract: The present disclosure provides a memory system with a non-volatile memory that includes a plurality of storage areas. Each storage may include a plurality of first storage groups in a first area and a plurality of second storage groups in a second area. The first area may support physical addressing. The second area may not support physical addressing. A memory controller of the memory system may perform a wear leveling process by swapping a first storage group having a first group write count with a second storage group having a second group write count. The first group write count may be a maximum group write count among a plurality of group write counts corresponding to the plurality of first storage groups. The second group write count may be a minimum group write count among a plurality of group write counts corresponding to the plurality of second storage groups.

Abstract: An integrated circuit for translating and reverse-translating the address included in a memory request is disclosed. The integrated circuit may first comprise a processor, a first boundary function, a second boundary function, and a component device. The processor is configured to transmit a memory request to a target module over a bus of the integrated circuit. The memory request requests access to one or more memory mapped resources and the memory request includes a physical address. The first boundary function is configured to translate the physical address to a relative address which operates in or applies to a different address space than an address space that the physical address operates in or applies to. The second boundary function is configured to translate the relative address to the physical address. The device is configured utilize the physical address transmitted by the second boundary function.

Abstract: In some exception flows, a device controller may need to store and subsequently recover a current state of a host queue. In these particular exception flows, recovering the current state of the host queue is complex due to the varying states a host queue may be in at the time of storing, including having pending commands in the host queue. Examples of such exception flows include low power modes in client SSDs and live migrations in enterprise SSDs. Using dummy host submission and completion queues during the host queue recovery process allows the device controller to efficiently operate even when there are pending commands in the host queue. The dummy queues may be stored in the HMB, internal DRAM, or any other system dummy buffer (i.e., in a different device or tenant).

Abstract: Methods and systems for managing data processing systems are disclosed. Data processing systems may be managed by monitoring for failure of a storage device. The storage device may be monitored by obtaining use data and diagnostic data for a storage device. The use data may be obtained to generate predicted future use data. The use data and the predicted future use data may be used to generate a use quantification. The use quantification and the diagnostic data may be ingested in a predictive algorithm to obtain a prediction of the operation of a storage device. The prediction may indicate the likelihood for failure of the storage device.