Abstract: A respective write cycle count for each of a plurality of data units of a memory device is obtained. Based on the respective write cycle count, whether a data unit of the plurality of data units satisfies a media management criterion is determined. Responsive to determining that the respective write cycle count satisfies the media management criterion, a media management operation every first constant cycle count on the data unit is performed. Responsive to determining that the respective write cycle count does not satisfy the media management criterion, a media management operation every second constant cycle count on the data unit is performed. The second constant cycle count is less than the first constant count.

Abstract: Methods, systems, and devices for maintaining sequentiality for media management of a memory sub-system are described. A plurality of read commands in connection with a set of media management operations for a plurality of transfer units are issued according to a read sequence. A plurality of entries associated with the set of media management operations are stored. A plurality of write commands in connection with the set of media management operations are issued based on the plurality of entries of the read sequence.

Abstract: A memory sub-system configured to be responsive to a time to live requirement for load commands from a processor. For example, a load command issued by the processor (e.g., SoC) can include, or be associated with, an optional time to live parameter. The parameter requires that the data at the memory address be available within the time specified by the time to live parameter. When the requested data is currently in the lower speed memory (e.g., NAND flash) and not available in the higher speed memory (e.g., DRAM, NVRAM), the memory sub-system can determine that the data cannot be made available with the specified time and optionally skip the operations and return an error response immediately.

Abstract: A method and apparatus for performing access control of a memory device with aid of additional physical address information are provided. The method includes: during a garbage collection procedure, reading valid data from a source block and writing the valid data into a destination block; updating at least one logical-to-physical address mapping table; receiving a first read request from a host device, wherein the first read request indicates reading at a first logical address; in response to the first read request, reading the valid data of the destination block according to the second physical address associated with the first logical address; receiving a second read request from the host device, wherein the second read request indicates reading at the first logical address; and in response to the second read request, reading the valid data of the source block according to the first physical address associated with the first logical address.

Abstract: A system and method for accessing cache lines of an N-way set associative cache distributed across local memory of compute elements. The set associative cache includes a plurality of sets, with each location in cacheable local memory mapped to one of the sets and each set including N locations for caching data blocks read from the cacheable memory. Each set is mapped to one of the local memories, when that local memory is not in use by local compute elements. A cache controller is configured to receive a read request, to identify a data block in the cacheable memory associated with the address, to determine if the identified data block is in cache in one of the local memories, and, if the identified data block is in cache in one of the local memories, to fetch the identified data block from the cache.

Abstract: Methods, systems, and devices for hardware-based coherency checking techniques are described. A memory sub-system with hardware-based coherency checking can include a coherency block that maintains a coherency lock and releases coherency upon completion of a write command. The coherency block can perform operations to lock coherency associated with the write command, monitor for completion of the write to the memory device(s), release the coherency lock, and update one or more records used to monitor coherency associated with the write command. A coherency command and coherency status can be provided through a dedicated hardware bridge, such as a bridge through a level-zero cache coupled with the coherency hardware.

Abstract: Methods, systems, and devices for page validity table colors for garbage collection are described. The memory system may obtain validity information and information associated with a characteristic for each page of a block of data and based on initiating a reorganization procedure on the block of data of the memory system. The memory system may move, for the reorganization procedure, a first set of pages of the block of data associated with a first value of the characteristic to a first portion of the memory system according to the validity information for the first set of pages. The memory system may move, for the reorganization procedure, a second set of pages of the block of data associated with a second value of the characteristic to a second portion of the memory system according to the validity information for the second set of pages.

Abstract: Disclosed are the SGL processing acceleration method and the storage device. The disclosed SGL processing acceleration method includes: obtaining the SGL associated with the IO command; generating the host space descriptor list and the DTU descriptor list according to the SGL; obtaining one or more host space descriptors of the host space descriptor list according to the DTU descriptor of the DTU descriptor list; and initiating the data transmission according to the obtained one or more host space descriptors.

Abstract: The size of a cache is modestly increased so that a short pointer to a predicted next memory address in the same cache is added to each cache line in the cache. In response to a cache hit, the predicted next memory address identified by the short pointer in the cache line of the hit along with an associated entry are pushed to a next faster cache when a valid short pointer to the predicted next memory address is present in the cache line of the hit.

Abstract: A data storage device includes a memory device including a plurality of endurance groups and a controller coupled to the memory device. The controller is configured to allocate tokens to the plurality of endurance groups, determine whether endurance group has sufficient tokens to perform an operation, and either deny the operation or approve the operation. The operation is selected from the group consisting of: garbage collection, relocation of data, and read scrubbing. Each operation has the same or different cost as another operation. The controller is further configured to set thresholds for each endurance group of the plurality of endurance groups and adjust a threshold for one or more endurance groups of the plurality of endurance groups. The controller is further configured to determine whether the operation will breach quality of service for other endurance groups.

Abstract: A flash memory controller includes a processor and a cache. When the processor receives a specific write command and specific data a host, the processor stores the specific data into a region of the cache, and the processor generates host-based cache information or flash-memory-based cache information to build or update/optimize a binary tree with fewer number of nodes to improve the searching speed of the binary tree, reducing computation overhead of multiple cores in the flash memory controller, and minimizing the number of accessing the cache to reduce the total latency wherein the host-based cache information may indicate dynamic data length and flash-memory-based cache information indicates the data length of one writing unit such as one page in flash memory chip.

Abstract: Disclosed are a storage device including a memory controller and a method of operating the memory controller. A storage device according to the technical idea of the present disclosure includes a write buffer for storing write data that is not grouped into a transaction, a non-volatile memory device including a journal buffer where journal logs are stored, a volatile memory device for temporarily storing first metadata, and a memory controller for updating the first metadata to the second metadata based on the journal log stored after the start of the checkpoint among the journal logs stored in the journal buffer.

Abstract: A storage system having high performance and high reliability includes a non-volatile storage device, a storage controller configured to control data to be read and written from and to the storage device using a storage function; and a volatile memory. In the reading and writing, the storage controller generates a log and stores the log in a log memory, writes the log stored in the memory to the storage device, and collects a capacity of the storage area of the memory storing the log written to the storage device. In collecting a free area of the memory, the storage controller executes a base image saving method of writing in the storage device in units of storage areas having a plurality of logs and collecting a free area, and a garbage collection method of writing in the storage device in units of logs and collecting a free area.

Abstract: A feature can be defined to allow data attributes to be dynamically assigned to data in a storage device. For example, a feature referred to as a “datagroup” is introduced. A datagroup is defined as a grouping of a range of local block addresses. A storage device can be divided into a number of datagroups. Each datagroup can have its own data attributes configuration, which can have a specified number of bits. A new command is defined to allow a host to dynamically assign attributes of datagroups of a storage device. For example, the command can provide for dynamically assigning datagroup attributes by sending a byte-mapping table in the command from the host to the storage device.

Abstract: A method and apparatus for identifying data that is to be accessible in a low power state of a data storage device, and store this data in a physical (or logical) block that will be accessible in a low power state of the data storage device. Low power accessible data may be identified by host metadata of the data, indicating access is needed in a low power state. In other embodiments, the data storage device may learn the power state in which data should be accessible. In these embodiments, a controller stores information regarding the power state of a namespace in which the data is stored as an indicator to make the data accessible in a low power state. Alternatively, the controller stores a previous power state in which the data was accessed as an indicator to make the data accessible in a low power state.

Abstract: Examples include selectively adjusting I/O Q-connections between an NVMe controller and a storage device in an NVMe system. In some examples, a utilization time of a host port in an NVMe controller is determined. In response to determining that the utilization time of the host port is lower than a host port utilization threshold and a number of I/O Q-connections at the storage device is less than an I/O Q-connection threshold for the storage device, a candidate list of storage devices is created, each storage devices included in the candidate list having an average service time greater than or equal to an average service time of a host port associated with the storage device. For each storage device included in the candidate list, processing time and I/O block size of I/O requests at the storage device is determined and a number of I/O Q-connections at the storage device is selectively adjusted based on the processing time and I/O block size of I/O requests at the storage device.

Abstract: A memory management system includes a cache invalidation logic configured to invalidate, based a cache invalidation event, cache entries within a cache memory by having each cache entry, of the cache entries within the cache memory, reference a respective dummy address from among dummy addresses within a dummy address space, wherein the cache memory is assigned to a memory, the memory has a memory address space associated therewith to provide access the memory, and each dummy address of the dummy addresses within the dummy address space is distinct from any address of the memory address space.

Abstract: The present disclosure relates to a storage device and an operating method thereof. The storage device includes a memory device including write-completed blocks storing data and free blocks each containing no data and a memory controller controlling the memory device to perform a garbage collection operation to store valid data stored in a victim block, among the write-completed blocks, in one of the free blocks based on the number of map segments including mapping information between logical addresses and physical addresses of the valid data, and erase counts of the free blocks.

Abstract: A method is described that includes determining, by a memory subsystem, that a garbage collection process is to be performed on a memory device and selecting a first candidate block stripe for folding into a first target block stripe in response to determining that the garbage collection process is to be performed. The method further includes determining, by the memory subsystem, that a physical-to-logical table stored in the first candidate block stripe is unavailable; reducing a write command rate, which controls a rate at which writes are fulfilled by the memory subsystem, in response to determining that the physical-to-logical table stored in the first candidate block stripe is unavailable; and performing folding of the first candidate block stripe into the first target block stripe using a logical-to-physical table.

Abstract: A processing device in a memory system identifies, while the memory device is in a first state condition, a plurality of workload conditions associated with the memory device, wherein the plurality of workload conditions comprise data reflecting a performance condition of the memory device. The processing device determines, while the memory device is in the first state condition, a host rate of a host system write performance for the memory device based on one or more workload conditions of the plurality of workload conditions. The processing device determines that one or more workload conditions of the plurality of workload conditions satisfies a first threshold criterion. Responsive to determining that the one or more workload conditions of the plurality of workload conditions satisfies the first threshold criterion, the processing device detects a change in a condition of the memory device from the first state to a second state.