Abstract: The memory system includes: a first sub-buffer for storing an address map table; a second sub-buffer configured to sequentially store logical addresses, and store a latest received logical address in a specific region; a third sub-buffer including write buffers configured to store a size of data corresponding to each of the logical addresses; a storage device comprising memory blocks; a processor configured to control the storage device to store the data in memory blocks corresponding to the logical addresses using a SLC method; and an address manager configured to select at least two logical addresses comprising the latest received logical address. The processor is configured to control the storage device to store data read from memory blocks corresponding to the at least two logical addresses in a memory block using an MLC method. The address manager is configured to release a write buffer corresponding to the latest received logical address.

Abstract: The present disclosure generally relates to creating new zones in a data storage device in a manner that ensures substantially even workload of the memory device storage locations. When receiving a zone open command in a zone namespace (ZNS) system, rather than randomly selecting an unopen zone, zones may be categorized based upon storage location workload so that any new zone that is opened utilizes the least utilized storage location. In so doing, generally even workload of the memory device storage locations is achieved.

Abstract: The present disclosure includes apparatuses and methods related to data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein a first number of commands are executed to transfer data between the first number of memory devices and the host via the first number of ports and a second number of commands are executed to transfer data between the first number of memory device and the second number of memory device via the second number of ports.

Abstract: A method, computer program product, and computer system for identifying a plurality of blocks. At least one heuristic associated with at least a portion of the plurality of blocks may be determined. It may be determined whether to compress at least the portion of the plurality of blocks based upon, at least in part, the at least one heuristic. At least the portion of the plurality of blocks may be compressed based upon, at least in part, the at least one heuristic.

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Abstract: A method, circuit, and system for managing wear levelling in non-volatile memory. First, an original physical block address (PBA) for a logical block address (LBA) of a write operation may be received. The original PBA is one of a set of PBAs for data blocks of a non-volatile memory array. Each of these PBAs may be uniquely mapped to a particular LBA using a multistage interconnection network (MIN). A swap PBA may next be determined for the LBA. The swap PBA may be selected from the set of PBAs uniquely mapped using the MIN. Then, the MIN may be configured to map the LBA to the swap PBA. Finally, data of a first data block stored at the original PBA may be swapped with data of a second data block stored at the swap PBA.

Abstract: A data storage device includes a memory device and a controller. The controller is configured to receive host commands, such as write commands. Upon determining that a received plurality of write commands are sequential, but includes one or more write commands that are unaligned with a memory granularity of the memory device, the one or more write commands are revised such that the one or more write commands are aligned with the memory granularity. The revised write command includes a first of the one or more write commands and a portion of a second of the one or more write commands. A beginning of the revised write command is aligned with the memory granularity and the end of the revised write command is also aligned with the memory granularity.

Abstract: An illustrative approach to managing snapshots streamlines how and when snapshots are generated in a storage management system, such that fewer snapshots may be generated without diminishing the scope of data protection. A novel unified-snapshot storage policy may govern snapshots for any number of subclients. A unified-snapshot job based on the unified-snapshot storage policy enables the illustrative storage management system to automatically discover relevant components and generate at most one snapshot per target logical unit number (“LUN”) in a storage array. Each snapshot may comprise the data of any number of subclients and/or clients in the storage management system. Accordingly, one unified-snapshot job may yield a minimum but sufficient number of snapshots comprising data of all subclients associated with the governing unified-snapshot storage policy. An enhanced storage manager may manage the unified-snapshot jobs.

Abstract: A data write system includes a processor circuit, a first memory, at least one register, and a second memory. The first memory is coupled to the processor circuit. The at least one register is configured to define at least one range. The second memory is coupled to the first memory. If a cache miss occurs and an access address of a reading command is in the at least one range in the second memory, a predetermined amount of data corresponding to the access address is written from the second memory into at least one first way of the first memory.

Abstract: An apparatus can include a memory device comprising a memory component and a memory controller that is coupled to the memory component. A memory searching component (MSC) is resident on the apparatus. The MSC can receive an external instruction indicative of performance of an operation to retrieve particular data from the memory component and issue, responsive to receipt of the instruction, a command to the memory controller to cause the memory controller to perform a read request invoking the memory component as part of performance of the operation in the absence of a further external instruction.

Abstract: A method for updating block addresses is provided. The method includes overwriting content of a first data block referenced by a first logical block address (LBA) with updated content. Prior to overwriting, the content of the first data block is stored in a first physical block corresponding to a first physical block address (PBA), a logical map maps the first LBA to a first middle block address (MBA), and a middle map maps the first MBA to the first PBA. After overwriting, the updated content of the first data block is stored in a second physical block corresponding to a second PBA and, in response to the overwriting, the middle map is updated to map the first MBA to the second PBA instead of the first PBA.

Abstract: The present invention extends to methods, systems, and computer program products for dynamically throttling host write data rates, for example, at SSDs. Host write data is received from a host at a host write data rate. The host write data is buffered in an SSD buffer at the host write data rate. Some host write data is transferred from the SSD buffer to NAND storage at an internal NAND data rate. A host write throttle is calculated at least based on the host data rate and the internal NAND data rate. The host write throttle defines a new (e.g., increased or decreased) host write data rate. The host write throttle is sent to the host requesting the host utilize the new host write data rate. When a new host write data rate is decreased, data transfer from SSD buffer to NAND storage can be allowed to “catch up”.

Abstract: The present disclosure generally relates to data storage devices, such as solid state drives. The data storage device includes a controller that includes a compression engine. The controller receives a ZNS append command to write data to a media, such as a non-volatile memory. The compression engine compresses data from a first number of logical blocks to second number of logical blocks. The compressed data is programmed to the media. The compressed data has a media logical block address and a host logical block address, where the media logical block address is the actual LBA where the ZNS append places the data on the media and the host logical block address is the location of the data stored on the media from the host's point of view. The host generates an index of the location of the stored data and the controller programs the index to the relevant location in the media.

Abstract: There are provided a storage device and an operating method thereof. The storage device includes: a nonvolatile memory device including a system block for storing firmware data including a program code of firmware, a signature in which the program code is encoded, and an authentication key; a volatile memory device configured to store operational firmware data; and a memory controller configured to, when power is applied to the storage device, store the firmware data as the operational firmware data in the volatile memory device, perform a firmware validity test for detecting whether the operational firmware data and the firmware data matches each other, in response to a test event, and perform a reset operation based on a result of the firmware validity test.

Abstract: The storage device includes: a memory device including a plurality of user blocks and a system block; a buffer memory for storing a physical-to-logical table, and a memory controller for controlling the memory device to update map data stored in the system block, based on the physical-to-logical table, and to store the updated map data in the system block, after logical addresses of the physical-to-logical table are all allocated.

Abstract: This application provides an information processing method, an apparatus, a device, and a system. The information processing method includes: A host chip determines first information, where the first information includes a first logical address set. The host chip generates first indication information, where the first indication information includes the first logical address set and a first physical address set that is determined based on a mapping relationship between a logical address and a physical address and that corresponds to the first logical address set, the first physical address set includes N physical addresses, the N physical addresses are in a one-to-one correspondence with N logical addresses included in the first logical address set, and N is an integer greater than or equal to 2. The host chip sends a first request to a storage chip connected to the host chip, where the first request includes the first indication information.

Abstract: A data storage device includes storage including a plurality of memory blocks and a controller configured to control operations of the plurality of memory blocks. The controller is configured to calculate a stress value of each of the plurality of memory blocks based on an erase completion count and an erase interruption count of the corresponding memory block.

Abstract: A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.

Abstract: Aspects of a storage device including a memory and a controller are provided which reduces or eliminates garbage collection in zoned namespace (ZNS) architectures by mapping zones to sub-blocks of blocks of the memory. Each zone includes a plurality of logical addresses. The controller determines a number of open zones, and maps the open zones to the sub-blocks in response to the number of open zones meeting a threshold. Thus, larger numbers of open blocks typically present in ZNS may be reduced, and increased block sizes due to scaling may be accommodated in ZNS. In some aspects, the controller receives a request from a host device to write data associated with the zones in sub-blocks, and maps each of the zones to at least one of the sub-blocks in response to the request. The request may indicate zones are partially unused. Thus, out of zone conditions may also be avoided.

Abstract: Systems and methods are disclosed for virtualized caches. For example, an integrated circuit (e.g., a processor) for executing instructions includes a virtually indexed physically tagged first-level (L1) cache configured to output to an outer memory system one or more bits of a virtual index of a cache access as one or more bits of a requestor identifier. For example, the L1 cache may be configured to operate as multiple logical L1 caches with a cache way of a size less than or equal to a virtual memory page size. For example, the integrated circuit may include an L2 cache of the outer memory system that is configured to receive the requestor identifier and implement a cache coherency protocol to disambiguate an L1 synonym occurring in multiple portions of the virtually indexed physically tagged L1 cache associated with different requestor identifier values.