Patents Examined by Khanh B. Duong
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Patent number: 8357931Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.Type: GrantFiled: December 28, 2007Date of Patent: January 22, 2013Assignee: Nvidia CorporationInventors: Brian S. Schieck, Howard Lee Marks
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Patent number: 8163613Abstract: A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps is used to form an array of second openings received partially over and partially offset from the array of first openings. Overlapping portions of the first and second openings are received over the storage node contacts. After both of the two masking steps, conductive material of the individual capacitor electrodes is deposited into the overlapping portions of each of the first and second openings. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.Type: GrantFiled: June 25, 2010Date of Patent: April 24, 2012Assignee: Micron Technology, Inc.Inventor: Fred D. Fishburn
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Patent number: 8129261Abstract: Methods for implanting ions into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, a method for implanting ions into a substrate includes providing a substrate into a processing chamber, the substrate comprising substrate surface having one or more features formed therein and each feature having one or more horizontal surfaces and one or more vertical surfaces, generating a plasma from a gas mixture including a reacting gas adapted to produce ions, depositing a material layer on the substrate surface and on at least one horizontal surface of the substrate feature, implanting ions from the plasma into the substrate by an isotropic process into at least one horizontal surface and into at least one vertical surface, and etching the material layer on the substrate surface and the at least one horizontal surface by an anisotropic process.Type: GrantFiled: October 27, 2009Date of Patent: March 6, 2012Assignee: Applied Materials, Inc.Inventors: Peter I. Porshnev, Matthew D. Scotney-Castle, Majeed A. Foad
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Patent number: 8053755Abstract: A strained semiconductor heterostructure (10) comprises an injection region comprising a first emitter layer (11) having p-type conductivity and a second emitter layer (12) having n-type conductivity, and a light generation layer (13) positioned between the first emitter layer (11) and the second emitter layer (12). An electron capture region (14) is positioned between the light generation layer (13) and the second emitter layer (12), said electron capture region comprising a capture layer (16) adjacent to the second emitter layer, and a confining layer (15) adjacent to said electron capture layer. According to the present invention, the widths and materials of the confining and capture layers (15, 16) are selected to provide energy difference between one of localized energy levels for electrons in the capture layer (16) and the conduction band bottom of the second emitter layer (12) equal to the energy of the optical phonon.Type: GrantFiled: September 19, 2005Date of Patent: November 8, 2011Assignee: OptoGaN OyInventors: Maxim A. Odnoblyudov, Vladislav E. Bougrov
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Patent number: 8022560Abstract: An overlay mark applicable in a non-volatile memory includes two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, two second Y-direction isolation structures, a first dielectric layer, and a conductive layer. The first X-direction isolation structures, the first Y-direction isolation structures, the second X-direction isolation structures, and the second Y-direction isolation structures are disposed in a substrate. The first X-direction isolation structures and the first Y-direction isolation structures are arranged to a first rectangle, the second X-direction isolation structures and the second Y-direction isolation structures are arranged to a second rectangle, and the second rectangle is located in the first rectangle. The first dielectric layer is disposed on a surface of the substrate. The conductive layer is disposed on the first dielectric layer.Type: GrantFiled: August 11, 2009Date of Patent: September 20, 2011Assignee: Winbond Electronics Corp.Inventors: Min-Hung Chen, Kao-Tsair Tsai
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Patent number: 8021965Abstract: The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.Type: GrantFiled: November 15, 2006Date of Patent: September 20, 2011Assignee: University of Norte Dame Du LacInventors: Gary H. Bernstein, Patrick Fay, Wolfgang Porod, Qing Liu
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Patent number: 8017464Abstract: As a method for constituting a pre-metal interlayer insulating film, such method is considered as forming a CVD silicon oxide-based insulating film having good filling properties of a silicon oxide film by ozone TEOS, reflowing the film at high temperatures to planarize it, then stacking a silicon oxide film having good CMP scratch resistance by plasma TEOS, and, further, planarizing it by CMP. However, it was made clear that, in a process for forming a contact hole, crack in the pre-metal interlayer insulating film is exposed in the contact hole, into which barrier metal intrudes to cause short-circuit defects. In the present invention, in the pre-metal process, after forming the ozone TEOS film over an etch stop film, the ozone TEOS film is once etched back so as to expose the etch stop film over a gate structure, and, after that, a plasma TEOS film is formed over the remaining ozone TEOS film, and then the plasma TEOS film is planarized by CMP.Type: GrantFiled: September 12, 2009Date of Patent: September 13, 2011Assignee: Renesas Electronics CorporationInventors: Masao Sugiyama, Yoshiyuki Kaneko, Yoshinori Kondo, Masayoshi Hirasawa
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Patent number: 8003458Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor.Type: GrantFiled: February 23, 2010Date of Patent: August 23, 2011Assignee: Infineon Technologies AGInventors: Frank Huebinger, Richard Lindsay
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Patent number: 7998796Abstract: The present invention provides a technique capable of suppressing variations in the height of each solder ball where an NSMD is used as a structure for each land. Vias that extend through a wiring board are provided. Lands are formed at the back surface of the wiring board so as to be coupled directly to the vias respectively. The lands are respectively formed so as to be internally included in openings defined in a solder resist. Half balls are mounted over the lands respectively. Namely, the present invention has a feature in that the configuration of coupling between each of the lands and its corresponding via both formed at the back surface of the wiring board is taken as a land on via structure and a configuration form of each land is taken as an NSMD.Type: GrantFiled: September 13, 2010Date of Patent: August 16, 2011Assignee: Renesas Electronics CorporationInventor: Tadatoshi Danno
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Patent number: 7994572Abstract: A MOSFET having a recessed channel and a method of fabricating the same. The critical dimension (CD) of a recessed trench defining the recessed channel in a semiconductor substrate is greater than the CD of the gate electrode disposed on the semiconductor substrate. As a result, the misalignment margin for a photolithographic process used to form the gate electrodes can be increased, and both overlap capacitance and gate induced drain leakage (GIDL) can be reduced.Type: GrantFiled: August 3, 2010Date of Patent: August 9, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Ji-young Kim
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Patent number: 7982256Abstract: A semiconductor memory device may have a DRAM cell mode and a non-volatile memory cell mode without a capacitor, including multiple transistors arranged in an array and having floating bodies, word lines connected to gate electrodes of the transistors, bit lines at a first side of the gate electrodes connected to drains of the transistors, source lines at a second side of the gate electrodes, different from the first side, and connected to sources of the transistors on the semiconductor substrate, and charge storage regions between the gate electrodes and the floating bodies.Type: GrantFiled: May 16, 2007Date of Patent: July 19, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Zong-Liang Huo, In-Seok Yeo
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Patent number: 7960203Abstract: A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.Type: GrantFiled: January 29, 2008Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Alejandro G. Schrott, Chung H. Lam, Eric A. Joseph, Matthew J. Breitwisch, Roger W. Cheek
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Patent number: 7955951Abstract: The present invention discloses an LED-laser lift-off method, which applies to lift off a transient substrate from an epitaxial layer grown on the transient substrate after a support substrate having an adhesion metal layer is bonded to the epitaxial layer. Firstly, the epitaxial layer is etched to define separation channels around each chip section, and the epitaxial layer between two separation channels is not etched but preserved to form a separation zone. Each laser illumination area only covers one illuminated chip section, the separation channels surrounding the illuminated chip section, and the separation zones surrounding the illuminated chip section. Thus, the adhesion metal layer on the separation channels is only heated once. Further, the outward stress generated by the illuminated chip section is counterbalanced by the outward stress generated by the illuminated separation zones, and the stress-induced structural damage on the chip section is reduced.Type: GrantFiled: November 13, 2009Date of Patent: June 7, 2011Assignee: High Power Opto, Inc.Inventors: Liang-Jyi Yan, Yea-Chen Lee
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Patent number: 7956445Abstract: A method of packaging an integrated circuit, including providing a lead frame having lead fingers, where the lead frame has a gold layer thereon on a top surface and a bottom surface. An integrated circuit die is attached to the lead frame. The gold layer is substantially removed from portions of the top surface of the lead frame. The integrated circuit die is wire bonded to the lead fingers with a plurality of wire stitches subsequent to substantially removing the gold. The die is encapsulated in a mold compound to form a packaged integrated circuit.Type: GrantFiled: August 15, 2006Date of Patent: June 7, 2011Assignee: Texas Instruments IncorporatedInventors: Takahiko Kudoh, Muhammad Faisal Khan
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Patent number: 7947971Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.Type: GrantFiled: April 8, 2010Date of Patent: May 24, 2011Assignee: Intel CorporationInventors: Prashant Majhi, Mantu Hudait, Jack T. Kavalieros, Ravi Pillarisetty, Marko Radosavljevic, Gilbert Dewey, Titash Rakshit, Willman Tsai
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Patent number: 7939876Abstract: A conductive strap spacer is formed within a buried strap cavity above an inner electrode recessed below a top surface of a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A portion of the conductive strap spacer is metallized by reacting with a metal to form a strap metal semiconductor alloy region, which is contiguous over the conductive strap spacer and a source region, and may extend to a top surface of the buried insulator layer along a substantially vertical sidewall of the conductive strap spacer. The conductive strap spacer and the strap metal semiconductor alloy region provide a stable electrical connection between the inner electrode of the deep trench capacitor and the source region of the access transistor.Type: GrantFiled: April 9, 2008Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Byeong Y. Kim
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Patent number: 7935966Abstract: A semiconductor device including, on at least one surface of a crystalline semiconductor substrate, at least one first amorphous semiconductor region doped with a first type of conductivity. The semiconductor substrate includes, on the same at least one surface, at least one second amorphous semiconductor region doped with a second type of conductivity, opposite the first type of conductivity. The first amorphous semiconductor region, insulated for the second amorphous semiconductor region by at least ore dielectric region in the contact with the semiconductor substrate, and the second amorphous semiconductor region form an interdigitated structure.Type: GrantFiled: January 18, 2006Date of Patent: May 3, 2011Assignee: Commissariat a l'Energie Atomique Et Aux Energies AlternativesInventors: Pierre Jean Ribeyron, Claude Jaussaud, Pere Roca I. Cabarrocas, Jerome Damon-Lacoste
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Patent number: 7932130Abstract: An integrated circuit package system includes: providing a die attach paddle with interconnection pads connected to a bottom surface of the die attach paddle; connecting a first device to the interconnection pads with a bond wire; connecting a lead to the interconnection pad or to the first device; encapsulating the first device and the die attach paddle with an encapsulation having a top surface; and etching the die attach paddle leaving a recess in the top surface of the encapsulation.Type: GrantFiled: August 1, 2008Date of Patent: April 26, 2011Assignee: Stats Chippac Ltd.Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay, Jairus Legaspi Pisigan
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Patent number: 7919345Abstract: A method is disclosed of fabricating micromechanical components provided with free-standing microstructures or membranes with predetermined mechanical stress, by initially depositing a sacrificial layer on a substrate followed by depositing a polysilicon layer on the sacrificial layer by a gaseous phase deposition and, finally, at least partial removal of the sacrificial layer. During deposition of the polysilicon layer, the process pressure selected determined the type of stress in the polysilicon layer, and the value of the stress is set by the process temperature selected. The process pressure is above the pressure range used in LPCVD reactors.Type: GrantFiled: November 21, 1995Date of Patent: April 5, 2011Assignee: Fraunhofer-Gesellschaft zur Forderung der angewandten Forschung e.V.Inventors: Mario Kirsten, Peter Lange, Beatrice Wenk, Werner Riethmueller
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Patent number: 7915179Abstract: In a method for forming an insulating film by performing plasma nitriding process to an oxide film on a substrate and then by annealing the substrate in a process chamber (51), the substrate is annealed under a low pressure of 667 Pa or lower. The annealing is performed for 5 or 45 seconds. The plasma nitriding process is performed by microwave plasma by using a planar antenna whereupon a multitude of slot holes are formed.Type: GrantFiled: November 2, 2005Date of Patent: March 29, 2011Assignee: Tokyo Electron LimitedInventors: Yoshihiro Sato, Tomoe Nakayama, Hiroshi Kobayashi, Yoshinori Osaki, Tetsuro Takahashi