Abstract: A high fill factor textured light emitting diode structure comprises: a first textured cladding and contact layer (2) comprising a doped III-V or II-VI group compound semiconductor or alloys of such semiconductors deposited by epitaxial lateral overgrowth (ELOG) onto a patterned substrate (1); a textured undoped or doped active layer (3) comprising a III-V or II-VI group semiconductor or alloys of such semiconductors and where radiative recombination of electrons aid holes occurs or intersubband transition occurs; and a second textured cladding and contact layer (4) comprising a doped III-V or II-VI group semiconductor or alloys of such semiconductors.

Abstract: An object of the present invention is to provide a semiconductor device which comprises a barrier film having a high etching selection ratio of the interlayer insulating film thereto, a good preventive function against the Cu diffusion, a low dielectric constant and excellent adhesiveness to the Cu interconnection and a manufacturing method thereof.

Abstract: A high-voltage semiconductor device and a method for making the same are provided. A high-voltage semiconductor device and a low-voltage semiconductor device are formed in a single substrate, a photolithography process that is required to form a high-voltage well region is omitted, and the well region of the high-voltage semiconductor is formed together with the well region of the low-voltage semiconductor device formed in another photolithography process.

Abstract: Methods, systems, and apparatuses for ball grid array land patterns are provided. A ball grid array land pattern includes a plurality of land pads and electrically conductive traces. The plurality of land pads is arranged in an array of rows and columns. A perimeter edge of the array includes a pair of adjacent oblong shaped land pads. An electrically conductive trace is routed between the pair of adjacent oblong shaped land pads from a land pad positioned in an interior of the array to a location external to the array. The oblong shaped land pads are narrower than standard round land pads, and thus provide more clearance for the routing of traces. The oblong shaped land pads enable more land pads of the land pattern array to be routed external to the array on each routing layer, and thus can save printed circuit board component and assembly costs.

Abstract: Devices and methods for plasma treated metal silicide layer formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a metal layer on a silicon substrate, exposing the metal layer to a plasma, and thermally treating the silicon substrate and the metal layer to form a metal silicide layer.

Abstract: A method of forming a magnetic memory device (and a resulting structure) on a low-temperature substrate, includes forming the memory device on a transparent substrate coated with a decomposable material layer subject to rapid heating resulting in a predetermined high pressure, and transferring the memory device to the low-temperature substrate.

Abstract: Systems and methods are disclosed for fabricating a device by forming a photosensitive area on a wafer; forming a control circuit adjacent the photosensitive area; and coating the photosensitive area with one or more film layers to form an optical filter. The filter provides a reduced leakage of an undesired wavelength onto the photosensitive area.

Abstract: An integrated circuit includes transistors in rows and columns providing an array, conductive lines in columns across the array, and resistivity changing material elements contacting the conductive lines and self-aligned to the conductive lines. The integrated circuit includes electrodes contacting the resistivity changing material elements, each electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.

Abstract: A method of forming a buffer layer for a nitride compound semiconductor light emitting device includes placing a sapphire (Al2O3) substrate in a reaction chamber; introducing a nitrogen source gas into a reaction chamber; and annealing the substrate in a state where the nitrogen source gas is introduced into the reaction chamber, to form an AIN compound layer on the substrate. The AIN compound layer having intermediate properties between those of the substrate and a semiconductor layer is formed between the substrate and the semiconductor layer. Thus, an interface space between the AIN compound layer and the buffer layer or the semiconductor layer that is to be formed on the AIN compound layer becomes smaller and a crystal stress also becomes smaller, thereby reducing a crack that may be generated due to differences in lattice constant and thermal expansion coefficient between the substrate and the semiconductor layer.

Abstract: Lanthanum-metal oxide dielectric layers and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices and systems. In an embodiment, a lanthanum aluminum oxide dielectric layer is formed using a trisethylcyclopentadionatolanthanum precursor and/or a trisdipyvaloylmethanatolanthanum precursor.

Abstract: An image sensor and a method for manufacturing the same are provided. The image sensor comprises at least one unit pixel, an interlayer dielectric, a color filter, a planarization layer, and a microlens. The microlens has a smooth surface after performing a plasma treatment process.

Abstract: The semiconductor device has: a ZnO-containing substrate containing Li; a zinc silicate layer formed above the ZnO-containing substrate; and a semiconductor layer epitaxially grown relative to the ZnO-containing substrate via the zinc silicate layer.

Abstract: A method for manufacturing a semiconductor device and a display device each including a thin film transistor which has excellent electric characteristics and high reliability, with high mass productivity. In a display device which includes a channel-etch inversely-staggered thin film transistor in which a microcrystalline semiconductor layer is used for a channel formation region, the microcrystalline semiconductor layer is formed of a stacked layer of a microcrystalline semiconductor film which is formed by a deposition method and can be a nucleus of crystal growth and an amorphous semiconductor film; a conductive film and a semiconductor film which forms a source region and a drain region and to which an impurity imparting one conductivity is added are formed over the amorphous semiconductor film; and the conductive film is irradiated with laser light.

Abstract: A method for forming a metal line in a semiconductor device may include forming a silicon (Si) monolayer as an etching prevention layer over an exposed portion of a lower metal layer and sidewalls of an upper metal layer, middle metal layer, and the entire surface of curved photoresist patterns.

Abstract: A leadframe strip production process provides encapsulated semiconductor chips with more than two annular rows of exposed leads by utilizing two types of frames, a leadframe to which IC devices are mounted, and a ring frame strip that is attached to the leadframe with a non-conductive adhesive. The leadframe includes die pads that receive the IC chip devices, and each die pad is positioned within multiple rows of connecting pads for connection with bonding pads of the device to be encapsulated. The connecting pads of the leadframe are arranged in an annular fashion, with inner rows being closer to the die pad and outer rows being farther from the die pad.

Abstract: A first film made of SiGe is formed over a support substrate whose surface layer is made of Si. A gate electrode is formed over a partial area of the first film, and source and drain regions are formed in the surface layer of the support substrate on both sides of the gate electrode. The gate electrode and source and drain regions constitute a first field effect transistor. A first stressor internally containing compressive strain or tensile strain is formed over the first film on both sides of the gate electrode of the first field effect transistor. The first stressor forms strain in a channel region.

Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.

Abstract: An apparatus and a method for packaging semiconductor devices. Disclosed are multi-die packaging apparatuses and techniques, especially useful for integrated circuit dice involving insulative substrates, such as silicon-on-insulator (SOI), where grounding of a base layer is not reasonably practical. Disclosed is a means for effectively grounding all layers of an integrated circuit device regardless of whether the device makes direct contact with a die-attach paddle.

Abstract: A multilevel phase change memory may be formed of a chalcogenide material formed between a pair of spaced electrodes. The cross-sectional area of the chalcogenide material may decrease as the material extends from one electrode to another. As a result, the current density decreases from one electrode to the other. This means that a higher current is necessary to convert the material that has the largest cross-sectional area. As a result, different current levels may be utilized to convert different amounts of the chalcogenide material to the amorphous or reset state. A distinguishable resistance may be associated with each of those different amounts of amorphous material, providing the opportunity to engineer a number of different current selectable programmable states.

Abstract: An electronic package includes a substrate (110, 310, 510) and a solder resist layer (120, 320, 520) over the substrate. The solder resist layer has a plurality of solder resist openings (121, 321, 521) therein. The electronic package further includes a finish layer (130, 330, 535) in the solder resist openings, an electrically conducting layer (140, 440) in the solder resist openings over the finish layer, and a solder material (150, 810) in the solder resist openings over the electrically conducting layer. The electrically conducting layer electrically connects the solder resist openings in order to enable the electrokinetic deposition of the solder material.