Abstract: A method of making a device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer to form a first photoresist pattern, rendering the first photoresist pattern insoluble to a solvent, forming a second photoresist layer over the first photoresist pattern, patterning the second photoresist layer to form a second photoresist pattern over the underlying layer, and etching the underlying layer using both the first and the second photoresist patterns as a mask.

Abstract: A conveyance system for a semiconductor wafer can be used without any change before and after a support plate is adhered to the wafer. Also, the finish accuracy of the wafer and the positioning accuracy between the wafer and the support plate can be relaxed, thus improving the manufacturing efficiency. The wafer is formed on its peripheral portion with a stepped portion, which is deeper than a finished thickness obtained by partial removal of the rear surface thereof and which can be eliminated by the partial removal of the wafer rear surface. The separation portion has a length which extends radially outward from a flat surface, and which is greater than a total sum of a maximum-minimum difference between the finish allowances of the diameters of the wafer and the support plate, and a maximum value of a positioning error between the wafer and the support plate generated upon adhesion thereof.

Abstract: A method for forming a MOS transistor includes providing a substrate having at least a gate structure formed thereon, performing a pre-amorphization (PAI) process to form amorphized regions in the substrate, sequentially performing a co-implantation process, a first ion implantation process, and a first rapid thermal annealing (RTA) process to form lightly doped drains (LDDs), forming spacers on sidewalls of the gate structure, and forming a source/drain.

Abstract: A stack of heat generating integrated circuit chips may be provided with intervening cooling integrated circuit chips. The cooling integrated circuit chips may include microchannels for the flow of the cooling fluid. The cooling fluid may be pumped using the integrated electroosmotic pumps. Removal of cooling fluid gases may be accomplished using integrated re-combiners in some embodiments.

Abstract: A crystalline film includes a first crystalline region having a first film thickness and a first crystalline grain structure; and a second crystalline region having a second film thickness and a second crystalline grain structure. The first film thickness is greater than the second film thickness and the first and second film thicknesses are selected to provide a crystalline region having the degree and orientation of crystallization that is desired for a device component.

Abstract: In one embodiment, the present invention includes a method for forming a sacrificial oxide layer on a base layer of a microelectromechanical systems (MEMS) probe, patterning the sacrificial oxide layer to provide a first trench pattern having a substantially rectangular form and a second trench pattern having a substantially rectangular portion and a lateral portion extending from the substantially rectangular portion, and depositing a conductive layer on the patterned sacrificial oxide layer to fill the first and second trench patterns to form a support structure for the MEMS probe and a cantilever portion of the MEMS probe. Other embodiments are described and claimed.

Abstract: A method for manufacturing a ferroelectric memory includes the steps of: forming an iridium film above a substrate; forming an iridium oxide layer on the iridium film; changing the iridium oxide layer into an amorphous iridium layer; oxidizing the amorphous iridium layer to form an iridium oxide portion; forming a ferroelectric film on the iridium oxide portion by a MOCVD method; and forming an electrode on the ferroelectric film.

Abstract: Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.

Abstract: A method includes providing a micro device wafer having micro devices supported by a wafer substrate and a multi-device lid substrate coupled to and spaced from the wafer substrate. The method further includes sawing through the multi-device lid substrate to a depth between the wafer substrate and the lid substrate.

Abstract: A method for fabricating a semiconductor device includes forming a sacrificial layer over a substrate, forming a contact hole in the sacrificial layer, forming a pillar to fill the contact hole. The pillar laterally extends up to a surface of the sacrificial layer and then the sacrificial layer is removed. The method further includes forming a gate dielectric layer over an exposed sidewall of the pillar, and forming a gate electrode over the gate dielectric layer. The gate electrode surrounds the sidewall of the pillar.

Abstract: An organic electroluminescence device includes a substrate; first electrodes arranged on the luminous portion of the substrate in a single direction; an insulating layer pattern formed on the first electrodes and the substrate in a lattice shape to define plural pixel openings on the first electrodes; partition layers formed on the insulating layer pattern, the partition layers intersecting the first electrodes perpendicularly; organic thin film layer formed on the pixel openings; second electrodes formed on the organic thin film layer to be perpendicular to the first electrodes; first bus electrode patterns formed on the pad portion of the substrate to be connected with the first electrodes; second bus electrode patterns formed on the pad portion of the substrate to be connected with the second electrodes and including a material for forming the second electrodes; and barrier films formed between the second bus electrode patterns.

Abstract: An integrated circuit package includes an angled one-piece substrate having a light source fixed to one area and a sensor die fixed to a second area, such that the light source is directed to illuminate the field of view of the sensor die when a surface of interest is imaged. The integrated circuit package is well suited for generating navigation information regarding movement relative to a surface. In one method of forming the integrated circuit package, the single-piece substrate is originally a generally flat lead frame to which the sensor die and light source are attached. After the components have been connected, the lead frame is bent to provide the desired light source-to-sensor angle. In an alternative method, the lead frame is pre-bent. For either method, optics may be connected to the integrated circuit package, thereby providing a module that includes the optics, the light source, the sensor and the packaging body.

Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

Abstract: An electro-mechanical device package includes a cap material permanently bonded to a device wafer encapsulating an electromechanical device. An intermediate material is used to bond the device and capping material together at a low temperature, and a structure including the intermediate material emanating from either the device or cap material, or both, provides an interlocking at the bonding interface. One package includes a reusable carrier wafer with a similar coefficient of thermal expansion as a mating material and a low cost cap wafer of different material than the device wafer. A method for temporarily bonding the cap material to the carrier wafer includes attaching the cap material to the carrier wafer and is then singulated to mitigate thermal expansion mismatch with the device wafer.

Abstract: A semiconductor memory includes a plurality of memory cell transistors each having a laminated gate. A method of producing the semiconductor memory includes the steps of: forming a plurality of element separation regions for separating the memory cell transistors; forming a first conductive layer through a gate oxide film; etching the first conductive layer to form a plurality of slits; forming spacers on sidewall portions of each of the slits; forming a second conductive layer through an insulating film; etching the first conductive layer, the second conductive layer, and the insulating film using one single mask to form the laminated gate; implanting a conductive impurity into the semiconductor substrate exposed on both sides of the laminated gate to form a drain/source region; forming an interlayer insulating film; forming a contact hole penetrating the interlayer insulating film to reach the semiconductor substrate.

Abstract: A passivation layer of AlN is deposited on a GaN channel HFET using molecular beam epitaxy (MBE). Using MBE, many other surfaces may also be coated with AlN, including silicon devices, nitride devices, GaN based LEDs and lasers as well as other semiconductor systems. The deposition is performed at approximately 150° C. and uses alternating beams of aluminum and remote plasma RF nitrogen to produce an approximately 500 ? thick AlN layer.

Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.

Abstract: The present invention provides to a gallium nitride (GaN) semiconductor and a method of manufacturing the same, capable of reducing crystal defects caused by a difference in lattice parameters, and minimizing internal residual stress. In particular, since a high-quality GaN thin film is formed on a silicon wafer, manufacturing costs can be reduced by securing high-quality wafers with a large diameter at a low price, and applicability to a variety of devices and circuit can also be improved.

Abstract: A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron, the substrate including a first substrate surface with a first surface region and a second surface region. The method also includes depositing a first set of nanoparticles on the first surface region, the first set of nanoparticles including a first dopant. The method further includes heating the substrate in an inert ambient to a first temperature and for a first time period creating a first densified film, and further creating a first diffused region with a first diffusion depth in the substrate beneath the first surface region.

Abstract: A method of manufacturing a semiconductor optical element, includes successively stacking a first semiconductor layer of a first conductivity type, an active layer, and a second semiconductor layer of a second conductivity type; applying a resist to the second semiconductor layer and patterning the resist into stripes by photolithography; forming recesses in the second semiconductor layer and a waveguide ridge adjacent to the recesses by dry-etching the second semiconductor layer only partially through the second semiconductor layer, using the resist as a mask; forming an insulating film on the waveguide ridge and in the recesses while leaving the resist; removing the insulating film from the resist so that the resist is exposed while the insulating film in the recess is left; removing the resist exposed; and forming an electrode on the waveguide ridge after removing the resist.