Abstract: A semiconductor device includes a Schottky diode on a silicon-on-insulator (SOI) substrate. The Schottky diode includes a guard ring with a first guard ring segment contacting a barrier region on a first lateral side of the barrier region, and a second guard ring segment contacting the barrier region on a second, opposite, lateral side of the barrier region. The first and second guard ring segments extend deeper in the semiconductor layer than the barrier region. The Schottky diode further includes a drift region contacting the barrier region, and may include a buried layer having the same conductivity type as the barrier region, extending at least partway under the drift region. The barrier region is isolated from the substrate dielectric layer of the SOI substrate by an isolation region having the same conductivity type as the guard ring. A metal containing layer is formed on the barrier region.

Abstract: A device includes a buried oxide layer disposed on a substrate, a first region disposed on the buried oxide layer and a first ring region disposed in the first region. The first ring region includes a portion of a guardring. The device further includes a first terminal region disposed in the first ring region, a second ring region disposed in the first region and a second terminal region disposed in the second ring region. The first terminal region is connected to an anode and the second terminal region is connected to a cathode. The first region has a graded doping concentration. The first region, the second ring region and the second terminal region have a first conductivity type, and the first ring region and the first terminal region have a second conductivity type. The first conductivity type is different from the second conductivity type.

Abstract: A semiconductor device including an element isolation in a trench formed in an upper surface of a semiconductor substrate, a trench isolation including a void in a trench directly under the element isolation, and a Cu wire with Cu ball connected to a pad on the semiconductor substrate, is formed. The semiconductor device has a circular trench isolation arrangement prohibition region that overlaps the end portion of the Cu ball in plan view, and the trench isolation is separated from the trench isolation arrangement prohibition region in plan view.

Abstract: A vertical semiconductor device includes a substrate, a drift region over the substrate, an upper region on the drift region, a top surface over the upper region and being substantially planar, and a series of implants of a second dopant in the upper region, such that each implant of the series of implants is located at a different depth below the top surface. The series of implants forms at least two gate region. The substrate and the drift region are doped with a first dopant of a first polarity. The second dopant has a second polarity opposite that of the first polarity. At least a portion of a channel region is provided between the at least two gate regions, and a conducting gap is defined within the channel region and between opposing sidewalls of the at least two gate regions.

Abstract: A semiconductor device includes a semiconductor layer including a super junction layer in which an n-type pillar layer and a p-type pillar layer are alternately disposed and a p-type withstand voltage holding structure formed on an upper layer part of the semiconductor layer to surround an active region. At least one withstand voltage holding structure overlaps with the super junction layer in a plan view. At least one withstand voltage holding structure overlapping with the super junction layer in a plan view has a gap which is an intermittent part of the withstand voltage holding structure.

Abstract: Semiconductor devices and methods of forming a semiconductor device that includes a polysilicon layer that may improve device reliability and/or a functioning of the device. An example device may include a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.

Abstract: A semiconductor structure includes a plurality of memory cells stacked up along a first direction. Each of the memory cells include a memory stack, connecting lines, and insulating layers. The memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. The connecting lines are extending along the first direction and covering side surfaces of the memory stack. The insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.

Abstract: A first light-emitting element and a second light-emitting element that have a resonance structure that causes output light from a light-emission functional layer to resonate between a reflective layer and a semi-transmissive reflective layer, and a pixel definition layer, and in which an aperture part is formed to correspond to each of the first light-emitting element and the second light-emitting element, are formed on a base. A first interval between the reflective layer and the semi-transmissive reflective layer in the first light-emitting element and a second interval between the reflective layer and the semi-transmissive reflective layer in the second light-emitting element are different, and a film thickness of the pixel definition layer is less than a difference between the first interval and the second interval.

Abstract: A 3D-NAND memory device is provided. The memory device includes a substrate, a bottom select gate (BSG) disposed over the substrate, a plurality of word lines positioned over the BSG with a staircase configuration and a plurality of insulating layers disposed between the substrate, the BSG, and the plurality of word lines. In the disclosed memory device, one or more first dielectric trenches are formed in the BSG and extend in a length direction of the substrate to separate the BSG into a plurality of sub-BSGs. In addition, one or more common source regions are formed over the substrate and extend in the length direction of the substrate. The one or more common source regions further extend through the BSG, the plurality of word lines and the plurality of insulating layers.

Abstract: A semiconductor device, including: a drift layer of a first conductivity type provided in a semiconductor base; a base layer of a second conductivity type provided in the semiconductor base at a front surface side thereof; a plurality of first trenches provided in the semiconductor base at a front surface side thereof, and having a plurality of first portions extending in a first direction to form a striped pattern; a second trench provided in the semiconductor base at a front surface side thereof, and having a plurality of second portions extending parallel to the first portions; a plurality of gate electrodes respectively provided in the first trenches; and a diode electrode provided in the second trench. The diode electrode includes: a plurality of inner electrodes provided in the second portions, and an outer electrode connecting the inner electrodes and surrounding ends of the first portions in a plan view.

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor layer including a first plane extending along a plane including a first axis and a second axis; a first electrode extending along the first axis; a second electrode extending along the second axis; and a third electrode above the first plane. The third electrode is electrically coupled to the first electrode and the second electrode, and includes a first portion, a second portion and a third portion. The first portion crosses the first electrode. The second portion crosses the second electrode. The third portion crosses the second electrode and is separate at a first end from the second portion.

Abstract: A three-dimensional (3D) memory structure includes a memory array formed on a side of a substrate, a far-back-end-of-line (FBEOL) structure formed on the memory array, and a back-end-of-line (BEOL) structure formed on another side of the substrate opposite the side on which the memory array and the BEOL structure are formed. Methodologies to fabricate the 3D memory structure are also disclosed and include forming the memory array on the substrate, forming the FBEOL on the memory array, flipping the substrate, and forming the BEOL on the opposite side of the substrate. Alternative 3D memory structures and fabrication methodologies are also disclosed.

Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.

Abstract: Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor disposed within at least one recess(es). The devices further include a logic area in which HV FETs, input/output (I/) FETs, and low voltage (LV)/core FETs are formed thereon. Other embodiments are also described.

Abstract: An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.

Abstract: A memory device includes a first conductor and a charge storage film extending along a first direction; a first semiconductor of a first conductive type; a second and third semiconductor each of a second conductive type; and a stack comprising a second conductor, a first insulator, and a third conductor sequentially stacked along the first direction and each extending along a second direction. The first conductor, the charge storage film, the first semiconductor, and the stack are arranged in this order along a third direction. The second semiconductor is in contact with the first semiconductor and the second conductor, between the second conductor or the first insulator and the charge storage film.

Abstract: In an example, a three-dimensional (3D) memory device includes a memory array structure including a first and a second memory array structures, a staircase structure between the first and a second memory array structures in a first lateral direction and including a first and a second staircase zones, and a bridge structure between the first and second staircase zones in a second lateral direction perpendicular to the first lateral direction. Each of the first and second staircase zones includes first and second sub-staircases arranged alternately. Each first sub-staircase includes ascending stairs at different depths. Each second sub-staircase includes descending stairs at different depths. At least one stair in each of the first and second sub-staircases is connected to at least one of the first and second memory array structures through the bridge structure.

Abstract: An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region buried in the semiconductor substrate providing a body and a second doped region in the semiconductor substrate providing a source. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region that may have void inclusion. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region. A pair of gate contacts are provided at each trench. The pair of gate contacts includes: a first gate contact extending into the first gate lobe at a location laterally offset from the void and a second gate contact extending into the second gate lobe at a location laterally offset from the void.

Abstract: A method includes depositing a first dielectric layer over a semiconductor substrate, depositing a first electrode layer over the first dielectric layer, etching the first electrode layer to form a first electrode and a second electrode laterally separated from the first electrode, depositing a Spin Orbit Torque (SOT) material on the first electrode and the second electrode, depositing Magnetic Tunnel Junction (MTJ) layers on the SOT material, depositing a second electrode layer on the MTJ layers, etching the SOT material to form a SOT layer extending from the first electrode to the second electrode, etching the MTJ layers to form an MTJ stack on the SOT layer, and etching the second electrode layer to form a top electrode on the MTJ stack.

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.