Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

Abstract: A semiconductor memory device may include a peripheral circuit structure including peripheral circuits integrated on a semiconductor substrate in a first region and a first keypad disposed in a second region; a stack provided on the first region of the peripheral circuit structure, the stack including a plurality of first conductive lines extending in a first direction and are vertically stacked; an upper insulating layer covering the stack; an interconnection layer provided on the upper insulating layer; a penetration plug spaced apart from the stack and is provided to penetrate the upper insulating layer to connect the interconnection layer to the peripheral circuits of the peripheral circuit structure; a molding structure provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction; and a penetration structure provided to penetrate the molding structure and vertically overlap with the first keypad.

Abstract: A vertical-type memory device includes a plurality of gate electrode layers spaced apart from one another and stacked on a substrate, and extending by different lengths in a first direction and forming a staircase structure, a first interlayer insulating layer covering the staircase structure of the plurality of gate electrode layers, and a plurality of gate contact plugs penetrating the interlayer insulating layer and respectively in contact with the gate electrode layers. The plurality of gate electrode layers include lower gate electrode layers disposed adjacently to the substrate, and upper gate electrode layers disposed on the lower gate electrode layers, so that the lower gate electrodes are between the substrate and the upper gate electrode layers. The plurality of gate contact plugs include lower gate contact plugs connected to the lower gate electrode layers, and upper gate contact plugs connected to the upper gate electrode layers.

Abstract: The present application provides a method for forming a sidewall protection layer in a heavily N-type doped shielding polysilicon for reducing gate to source leakage in a shielded gate trench metal-oxide-semiconductor field effect transistor (SGT MOSFET). In the process of forming a shielding polysilicon sidewall is manufactured by using a secondary oxidation layer forming process, so as to increase a thickness of an oxide in a top region of the shielding polysilicon and a thickness of an oxide of a trench sidewall in a transition region between the shielding polysilicon and an N-type doped gate polysilicon to solve the problem of serious gate to source leakage current.

Abstract: A semiconductor device includes a semiconductor layer having a front surface on which a transistor is provided and a back surface opposite to the front surface, and a conductive member that penetrates through the semiconductor layer. In the semiconductor device, between a second plane including the back surface and a third plane, a solid material that is an insulator is provided between the conductive member and the semiconductor layer, and, between a first plane including the front surface and the third plane, a hollow part is provided between the conductive member and the semiconductor layer, and a center of the hollow part in a direction crossing the first plane and the second plane is positioned between the first plane and the third plane.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer disposed over a base substrate, and an active layer disposed on the channel layer. A source contact and a drain contact are over the active layer and are laterally spaced apart from one another along a first direction. A gate electrode is arranged on the active layer between the source contact and the drain contact. A passivation layer is arranged on the active layer and laterally surrounds the source contact, the drain contact, and the gate electrode. A conductive structure is electrically coupled to the source contact and is disposed laterally between the gate electrode and the source contact. The conductive structure extends along an upper surface and a sidewall of the passivation layer.

Abstract: A semiconductor storage device includes a substrate, a pad provided above the substrate, first conductor layers stacked along a direction between the substrate and the pad, a second conductor layer provided above the first conductor layers, a semiconductor layer extending along the direction in the first conductor layers and in contact with the second conductor layer, a charge storage layer provided between the semiconductor layer and the first conductor layers, a contact extending along the direction between the substrate and the pad, and a wiring layer including a first portion in contact with the second conductor layer, a second portion in contact with the contact, and a third portion connecting the first portion and the second portion. The first portion and the second portion are located at a height between a height of the second conductor layer and a height of the third portion along the direction.

Abstract: According to one or more embodiments, a method for manufacturing a semiconductor device includes alternately stacking a first film and a second film on an object to form a multilayer film, then forming a stacked body and a recess by partially removing the multilayer film. A dielectric layer is then formed by applying a composite material to the recess to fill the recess with the dielectric layer. The composite material includes an inorganic material and an organic material. The dielectric layer is then exposed to an oxidizing gas to oxidize the inorganic material and to remove at least part of the organic material from the dielectric layer.

Abstract: A semiconductor device includes first to fourth electrodes, a semiconductor portion, and first and second insulating films. The semiconductor portion includes first to third semiconductor layers. The second electrode is in contact with the third semiconductor layer and is spaced from the second semiconductor layer, the third semiconductor layer, and the second electrode. The first insulating film covers the third electrode. The fourth electrode is connected to the second electrode, and is spaced from the first semiconductor layer and the third electrode. The second insulating film is provided on a side surface of the fourth electrode, faces the first semiconductor layer through an air gap, and increases in thickness toward the first direction.

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes forming multiple openings in staircase regions, periphery device regions, and substrate contact regions of a 3D NAND memory device. The openings can be formed by a photolithography process followed by multiple etching processes. The openings can include complete openings that expose the underlying layer and mid-way openings where a remaining portion of the photoresist still exists between the opening and the underlying layer. The remaining portion of the photoresist can delay the etching process in the shorter openings for the upper level staircase structure during the formation of the deeper openings for the lower level staircase structure. Conductive material is deposited into the openings to form contact structures for structures such as substrate contact pads, upper and lower level staircase structures, and/or peripheral devices.

Abstract: A laterally diffused metal oxide semiconductor device can include: a base layer; a source region and a drain region located in the base layer; a first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; a second conductor at least partially located on the voltage withstanding layer; and a source electrode electrically connected to the source region, where the first and second conductors are spatially isolated, and the source electrode at least covers a space between the first and second conductors.

Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure and laterally dividing the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first memory array structure and the second memory array structure. The first staircase zone includes a first pair of staircases facing each other in a first lateral direction and at different depths. Each staircase includes a plurality of stairs. At least one stair in the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

Abstract: Some embodiments include a memory cell having a conductive gate comprising ruthenium. A charge-blocking region is adjacent the conductive gate, a charge-storage region is adjacent the charge-blocking region, a tunneling material is adjacent the charge-storage region, and a channel material is adjacent the tunneling material. Some embodiments include an assembly having a vertical stack of alternating insulative levels and wordline levels. The wordline levels contain conductive wordline material which includes ruthenium. Semiconductor material extends through the stack as a channel structure. Charge-storage regions are between the conductive wordline material and the channel structure. Charge-blocking regions are between the charge-storage regions and the conductive wordline material. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.

Abstract: The application relates to a semiconductor transistor device, having a source region, a body region including a channel region extending in a vertical direction, a drain region, a gate region arranged aside the channel region in a lateral direction, and a body contact region made of an electrically conductive material, wherein the body contact region forms a body contact area, the body contact region being in an electrical contact with the body region via the body contact area, and wherein the body contact area is tilted with respect to the vertical direction and the lateral direction.

Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure and laterally dividing the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first and second memory array structures. The bridge structure includes a lower wall portion and an upper staircase portion. The first staircase zone includes a first pair of staircases facing each other in a first lateral direction and at different depths. Each staircase includes stairs. At least one stair in the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

Abstract: The present disclosure relates to a transistor device. The transistor device includes a plurality of first source/drain contacts disposed over a substrate. A plurality of gate structures are disposed over the substrate between the plurality of first source/drain contacts. The plurality of gate structures wrap around the plurality of first source/drain contacts in a plurality of closed loops. A second source/drain contact is disposed over the substrate between the plurality of gate structures. The second source/drain contact continuously wraps around the plurality of gate structures as a continuous structure.

Abstract: A high-voltage semiconductor device integrates a MOS transistor with a Schottky barrier diode. The MOS transistor has a semiconductor substrate of a first conduction type, a well of a second conduction, a body of the first conduction type, and a doped source of the second type. A control gate formed above the body controls electric connection between the doped source and the well. The Schottky barrier diode has a metal, functioning to be an anode of the Schottky barrier diode and contacting the well to form a Schottky barrier junction therebetween.

Abstract: A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.

Abstract: A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.