Abstract: A method for forming a memory device is provided. The memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.

Abstract: A method for forming a semiconductor device includes forming a metal layer and a spacer adjacent to the metal layer. The spacer includes a composite-dielectric layer including a composite-dielectric material. A composition of the composite-dielectric material is a mixture of a composition of a first dielectric material and a composition of a second dielectric material different from the first dielectric material.

Abstract: A nano-wall integrated circuit structure with high integration density is disclosed, which relates to the fields of microelectronic technology and integrated circuits (IC). Based on the different device physical principles with MOSFETs in traditional ICs, the nano-wall integrated circuit unit structure (Nano-Wall FET, referred to as NWaFET) with high integration density can improve the integration of the IC, significantly shorten the channel length, improve the flexibility of the device channel width-to-length ratio adjustment, and save chip area.

Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including gate electrodes sequentially stacked on the substrate, a source structure between the electrode structure and the substrate, vertical semiconductor patterns passing through the electrode structure and the source structure, a data storage pattern between each of the vertical semiconductor patterns and the electrode structure, and a common source pattern between the source structure and the substrate. The common source pattern has a lower resistivity than the source structure and is connected to the vertical semiconductor patterns through the source structure.

Abstract: A semiconductor memory device according to an embodiment includes a semiconductor substrate, a first insulating layer, a second insulating layer, the first insulating layer between the semiconductor substrate and the second insulating layer, a semiconductor layer between the first insulating layer and the second insulating layer, the semiconductor layer extending in a first direction parallel to a surface of the semiconductor substrate, a gate electrode layer extending in a direction perpendicular to the surface; a first insulating film between the semiconductor layer and the gate electrode layer, a second insulating film between the first insulating film and the gate electrode layer the second insulating film in contact with the first insulating layer and the second insulating layer, a polycrystalline silicon region between the first insulating film and the second insulating film; and a metal film between the polycrystalline silicon region and the second insulating film containing titanium and silicon.

Abstract: A method of fabricating an electronic power module by additive manufacturing, the electronic module including a substrate having an electrically insulating plate presenting opposite first and second faces, with a first metal layer arranged directly on the first face of the insulating plate, and a second metal layer arranged directly on the second face of the insulating plate. At least one of the metal layers is made by a step of depositing a thin layer of copper and a step of annealing the metal layer, and the method further includes a step of forming at least one thermomechanical transition layer on at least one of the first and second metal layers, the at least one thermomechanical transition layer including a material presenting a coefficient of thermal expansion that is less than that of the metal of the metal layer.

Abstract: A semiconductor memory device includes a substrate, a plurality of first conductive layers, a second conductive layer, a first pillar, and a second pillar. The plurality of first conductive layers are stacked over the substrate in a first direction. The second conductive layer is disposed over the plurality of first conductive layers. The first pillar extends inside the plurality of first conductive layers in the first direction. The first pillar includes a first semiconductor portion including a first semiconductor of single-crystal. The second pillar extends inside the second conductive layer in the first direction. The second pillar includes an insulating portion serving as an axis including an insulator and a second semiconductor portion which is disposed on an outer circumference of the insulating portion in view of the first direction. The second semiconductor portion is in contact with the first semiconductor portion and includes a second semiconductor of poly-crystal.

Abstract: Techniques for forming gate last VFET devices are provided. In one aspect, a method of forming a VFET device includes: forming a stack on a wafer including: i) a doped bottom source/drain, ii) sacrificial layers having layers of a first sacrificial material with a layer of a second sacrificial material therebetween, and iii) a doped top source/drain; patterning trenches in the stack to form individual gate regions; filling the trenches with a channel material to form vertical fin channels; selectively removing the layers of the first sacrificial material forming first cavities in the gate regions; forming gate spacers in the first cavities; selectively removing the layer of the second sacrificial material forming second cavities in the gate regions; and forming replacement metal gates in the second cavities. A VFET device is also provided.

Abstract: A memory cell includes a substrate and a body including plural layers. The body has an inner body and an outer body, and the body is formed on top of the substrate. A nanotube trench is formed vertically in the body and extends to the substrate. A nanotube structure is formed in the nanotube trench. The nanotube trench divides the body into the inner body and the outer body and the nanotube structure is mechanically separated from the inner body and the outer body by a tunnel oxide layer, a charge trapping layer, and a blocking oxide layer.

Abstract: An electronic device, a lead frame, and a method, including providing a lead frame with a Y-shaped feature having branch portions connected to a dam bar in a prospective gap in an equally spaced repeating lead pitch pattern, and a set of first leads extending parallel to one another along a first direction and spaced apart from one another along a second direction in lead locations of the repeating lead pitch pattern, attaching a semiconductor die to a die attach pad of the lead frame, attaching bond wires between bond pads of the semiconductor die, and the first leads, enclosing first portions of the first leads, the die attach pad, and a portion of the semiconductor die in a package structure, and performing a dam bar cut process that cuts through portions of the dam bar between the lead locations of the repeating lead pitch pattern.

Abstract: A mask layer is formed over a semiconductor device. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening that exposes a portion of the first layer and a portion of the ILD. A first etching process is performed to etch the opening partially into the first layer and partially into the ILD. A liner layer is formed in the opening after the first etching process has been performed. A second etching process is performed after the liner layer has been formed. The second etching process extends the opening downwardly through the first layer and through the gate structure. The opening is filled with a second layer after the second etching process has been performed.

Abstract: A bonding apparatus includes a bond head structure, an optical unit and an actuator unit. The bond head structure includes a bond head collet, a connecting unit to which the bond head collet is attached and a look-through passage extending through the bond head collet and the connecting unit along a central axis of the bond head structure. In use, the bond head collet holds an electrical component to be bonded to a bonding area of a base member and the optical unit is positioned relative to the bond head structure to view and inspect the electrical component through the look-through passage of the bond head structure. The actuator unit moves the connecting unit of the bond head structure based on the inspection of the electrical component by the optical unit, to align the electrical component with the bonding area of the base member.

Abstract: A three-dimensional semiconductor device includes a first substrate; a plurality of first transistors on the first substrate; a second substrate on the plurality of first transistors; a plurality of second transistors on the second substrate; and an interconnection portion electrically connecting the plurality of first transistors and the plurality of second transistors. Each of the plurality of first transistors includes a first gate insulating film on the first substrate and having a first hydrogen content. Each of the plurality of second transistors includes a second gate insulating film on the second substrate and having a second hydrogen content. The second hydrogen content is greater than the first hydrogen content.

Abstract: The present application relates to a semiconductor transistor device that includes a Schottky diode electrically connected in parallel to a body diode formed between a body region and a drift region. A diode junction of the Schottky diode is formed adjacent to the drift region and is arranged vertically above a lower end of the body region.

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a first dielectric layer over a substrate; depositing a sacrificial layer over the first dielectric layer; depositing a second dielectric layer over the sacrificial layer; depositing an erase gate electrode layer over the second dielectric layer; etching a memory hole in the erase gate electrode layer, the sacrificial layer, and the first and second dielectric layers; and forming a semiconductor layer in the memory hole.

Abstract: Techniques herein include methods of forming circuits by combining multiple substrates. High voltage devices are fabricated on a first wafer, and low voltage devices and/or memory are then fabricated on a second wafer and/or third wafer.

Abstract: An SBD of a JBS structure has on a front side of a semiconductor substrate, nickel silicide films in ohmic contact with p-type regions and a FLR, and a titanium film forming a Schottky junction with an n?-type drift region. A thickness of each of the nickel silicide films is in a range from 300 nm to 700 nm. The nickel silicide films each has a first portion protruding from the front surface of the semiconductor substrate in a direction away from the front surface of the semiconductor substrate, and a second portion protruding in the semiconductor substrate from the front surface of the semiconductor substrate in a depth direction. A thickness of the first portion is equal to a thickness of the second portion. A width of the second portion is wider than a width of the first portion.

Abstract: The present application discloses a semiconductor device with a programmable unit and a method for fabricating the semiconductor device. The semiconductor device includes a substrate comprising a first region and a second region; a first semiconductor element positioned in the first region of the substrate; a second semiconductor element positioned in the first region of the substrate and electrically coupled to the first semiconductor element; and a programmable unit positioned in the second region and electrically connected to the first semiconductor element.

Abstract: Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.