Patents Examined by Khatib A Rahman
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Patent number: 11527630Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a first dielectric layer over a substrate; depositing a sacrificial layer over the first dielectric layer; depositing a second dielectric layer over the sacrificial layer; depositing an erase gate electrode layer over the second dielectric layer; etching a memory hole in the erase gate electrode layer, the sacrificial layer, and the first and second dielectric layers; and forming a semiconductor layer in the memory hole.Type: GrantFiled: June 24, 2020Date of Patent: December 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Pin Chang, Chien-Hung Liu, Chih-Wei Hung
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Patent number: 11527545Abstract: Techniques herein include methods of forming circuits by combining multiple substrates. High voltage devices are fabricated on a first wafer, and low voltage devices and/or memory are then fabricated on a second wafer and/or third wafer.Type: GrantFiled: August 31, 2020Date of Patent: December 13, 2022Assignee: Tokyo Electron LimitedInventors: H. Jim Fulford, Mark I. Gardner
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Patent number: 11527634Abstract: An SBD of a JBS structure has on a front side of a semiconductor substrate, nickel silicide films in ohmic contact with p-type regions and a FLR, and a titanium film forming a Schottky junction with an n?-type drift region. A thickness of each of the nickel silicide films is in a range from 300 nm to 700 nm. The nickel silicide films each has a first portion protruding from the front surface of the semiconductor substrate in a direction away from the front surface of the semiconductor substrate, and a second portion protruding in the semiconductor substrate from the front surface of the semiconductor substrate in a depth direction. A thickness of the first portion is equal to a thickness of the second portion. A width of the second portion is wider than a width of the first portion.Type: GrantFiled: April 19, 2021Date of Patent: December 13, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventor: Naoyuki Ohse
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Patent number: 11521978Abstract: The present application discloses a semiconductor device with a programmable unit and a method for fabricating the semiconductor device. The semiconductor device includes a substrate comprising a first region and a second region; a first semiconductor element positioned in the first region of the substrate; a second semiconductor element positioned in the first region of the substrate and electrically coupled to the first semiconductor element; and a programmable unit positioned in the second region and electrically connected to the first semiconductor element.Type: GrantFiled: June 28, 2021Date of Patent: December 6, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Cheng-Ling Yang
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Patent number: 11522053Abstract: Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.Type: GrantFiled: December 3, 2021Date of Patent: December 6, 2022Assignees: Amplexia, LLC, X-FAB Global Services GmbHInventors: Brendan Toner, Zhengchao Liu, Gary M. Dolny, William R. Richards, Manoj Chandrika Reghunathan, Stefan Eisenbrandt, Christoph Ellmers
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Patent number: 11508809Abstract: The present disclosure discloses a semiconductor device and a preparation method thereof. The semiconductor device includes: an N+ substrate, a plurality of openings opening toward a back surface formed in the N+ substrate; an N? epitaxial layer formed on the N+ substrate, the N? epitaxial layer including: an active area epitaxial layer including a plurality of P++ area rings and a plurality of groove structures, wherein single groove structure is formed on single P++ area ring; a terminal area epitaxial layer including an N+ field stop ring and a plurality of P+ guard rings; a Schottky contact formed on the active area epitaxial layer, a passivation layer formed on the terminal area epitaxial layer, and ohmic contacts formed on the back surface of the N+ substrate and in the plurality of openings.Type: GrantFiled: September 12, 2018Date of Patent: November 22, 2022Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Yidan Tang, Xinyu Liu, Yun Bai, Shengxu Dong, Chengyue Yang
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Patent number: 11502230Abstract: A light emitting device including first, second, and third light emitting parts disposed one over another and each including a first-type semiconductor layer, an active layer, and a second-type semiconductor layer, a first conductive pattern at least partially disposed between the second and third light emitting parts, the first conductive pattern including a first portion electrically coupled with at least one of the first-type and second-type semiconductor layers of the first and second light emitting parts, and a second portion extending from the first portion and disposed on one surface of the second light emitting part between the second and third light emitting parts, and a second conductive pattern disposed on the third light emitting part and electrically coupled with the first conductive pattern, in which the second conductive pattern at least partially overlaps with the second portion of the first conductive pattern.Type: GrantFiled: October 30, 2019Date of Patent: November 15, 2022Assignee: SEOUL VIOSYS CO., LTD.Inventors: Seong Gyu Jang, Chan Seob Shin, Seom Geun Lee, Ho Joon Lee, Jong Hyeon Chae
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Patent number: 11502140Abstract: A display apparatus including an organic light-emitting display panel and a touch sensing unit disposed on the organic light-emitting display panel is disclosed. The touch sensing unit includes a touch electrode and a wiring part connected to the touch electrode. The wiring part of the touch sensing unit passes a protruding member disposed on a non-display region of the organic light-emitting display panel, and forms a first wiring part which does not overlap the protruding member, a second wiring part overlapping the protruding part, and a connection wiring part disposed between the first and second wiring parts and having a wiring width less than the first and second wiring parts so as to overlap an edge of the protruding member.Type: GrantFiled: July 30, 2020Date of Patent: November 15, 2022Assignee: Samsung Display Co., Ltd.Inventors: Chiwook An, Miyoung Kim, Jongseok Kim, Kiho Bang
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Patent number: 11502045Abstract: An electronic device includes a semiconductor die, an enclosure, leads extending outwardly from the enclosure and electrically connected to the semiconductor die, and wherein the leads have a reduced cross-sectional area along a longitudinal length of the lead. The electronic device is designed to reduce the occurrence of crack formation between the leads and a printed circuit board.Type: GrantFiled: January 23, 2019Date of Patent: November 15, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Amirul Afiq bin Hud, Wei Fen Sueann Lim, Adi Irwan Herman
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Patent number: 11495497Abstract: An embodiment of a semiconductor switch structure includes source contacts, drain contacts, gates and fins. The contacts and gates are elongated in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction. The gates are interspersed between the contacts. The fins underlie both the contacts and the gates. The fins are elongated in the second direction and are spaced apart from each other in the first direction. A contact via extends through one of the contacts without contacting a gate or a fin. A gate via extends through one of the gates without contacting a contact or a fin. A contact-gate via is in contact with both a contact and a gate but not a fin.Type: GrantFiled: February 5, 2021Date of Patent: November 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Ho Che Yu
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Patent number: 11489115Abstract: A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.Type: GrantFiled: May 3, 2021Date of Patent: November 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chieh Huang, Jieh-Jang Chen, Feng-Jia Shiu, Chern-Yow Hsu
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Patent number: 11482601Abstract: A vertical trench shield device can include a plurality of gate structures and a termination structure surrounding the plurality of gate structures. The plurality of gate structures can include a plurality of gate regions and a corresponding plurality of gate shield regions. The plurality of gate structures can be disposed between the plurality of source regions, and extending through the plurality of body regions to the drift region. The plurality of gate structures can be separated from each other by a first predetermined spacing in a core area. A first set of the plurality of gate structures can extend fully to the termination structure. The ends of a second set of the plurality of gate structures can be separated from the termination structure by a second predetermined spacing. The first and second spacings can be configured to balance charge in the core area and the termination area in a reverse bias condition.Type: GrantFiled: March 16, 2021Date of Patent: October 25, 2022Assignee: Vishay-Siliconix, LLCInventors: Jun Hu, M. Ayman Shibib, Misbah Azam, Kyle Terrill
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Patent number: 11476271Abstract: A memory device includes a substrate, a first dielectric structure, a second dielectric structure, a channel structure, a source structure, and a drain structure. The first dielectric structure and the second dielectric structure are disposed on the substrate, and are spaced apart from each other in a first direction. The channel structure interconnects the first dielectric structure and the second dielectric structure. The source structure and the drain structure are on opposite ends of the channel structure, and are respectively embedded in the first dielectric structure and the second dielectric structure, wherein a ratio in length along the first direction of the source structure to the first dielectric structure is between 0.3 and 0.4.Type: GrantFiled: November 4, 2020Date of Patent: October 18, 2022Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventor: Be-Shan Tseng
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Patent number: 11469240Abstract: A semiconductor device includes a metal layer and a spacer arranged adjacent to the metal layer. The spacer includes a composite-dielectric layer including a composite-dielectric material. A composition of the composite-dielectric material is a mixture of a composition of a first dielectric material and a composition of a second dielectric material different from the first dielectric material.Type: GrantFiled: June 1, 2020Date of Patent: October 11, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Liheng Liu, Chuan Yang, Shuangshuang Peng
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Patent number: 11462637Abstract: According to one embodiment, a semiconductor device includes first, second, and third conductive members, a semiconductor member, and a first insulating member. The semiconductor member includes a first semiconductor region provided on the first conductive member, a second semiconductor region provided on a portion of the first semiconductor region, and a third semiconductor region provided on the second semiconductor region. An impurity concentration in the third semiconductor region is greater than in the first semiconductor region. The second conductive member includes a first conductive portion electrically connected to the second and third semiconductor regions. The third conductive member is provided on an other portion of the first semiconductor region. At least a portion of the first insulating member is between the semiconductor member and the third conductive member.Type: GrantFiled: March 4, 2021Date of Patent: October 4, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Shotaro Baba, Yusuke Kobayashi, Hiroaki Katou, Toshifumi Nishiguchi
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Patent number: 11450681Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.Type: GrantFiled: April 9, 2020Date of Patent: September 20, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Haemin Lee, Jongwon Kim, Shinhwan Kang, Kohji Kanamori, Jeehoon Han
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Patent number: 11444111Abstract: According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, and a transparent member including a first surface and a second surface, where the second surface of the transparent member is coupled to the image sensor die via one or more dam members such that an empty space exists between an active area of the image sensor die and the second surface of the transparent member. The image sensor package includes a light blocking member coupled to or defined by the transparent member.Type: GrantFiled: July 9, 2019Date of Patent: September 13, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yu-Te Hsieh, I-Lin Chu
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Patent number: 11444092Abstract: The present technology includes a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first semiconductor layer, a cell stack and a peripheral stack each disposed on the first semiconductor layer, a first slit structure extending in a first direction and penetrating the cell stack and the peripheral stack, a penetration structure penetrating the peripheral stack and being spaced apart from the first slit structure, and a support structure penetrating the peripheral stack. The support structure includes first sidewall portions spaced apart from each other and a second sidewall portion connecting the first sidewall portions to each other, and the penetration structure is disposed between the first sidewall portions.Type: GrantFiled: June 10, 2020Date of Patent: September 13, 2022Assignee: SK Hynix Inc.Inventor: Sang Bum Lee
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Patent number: 11437393Abstract: A memory array includes a plurality of memory cells stacked up along a first direction. Each of the memory cells include a memory stack, connecting lines, and insulating layers. The memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. The connecting lines are extending along the first direction and covering side surfaces of the memory stack. The insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.Type: GrantFiled: May 28, 2020Date of Patent: September 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chih Lai, Chung-Te Lin
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Patent number: 11437388Abstract: A semiconductor memory device includes a substrate, a first stack, a plurality of first columnar portions, a second stack, a plurality of second columnar portions, and a third stack. In the first stack, first conductive layers and first insulating layers are alternately stacked in a thickness direction of the substrate. Each of the plurality of first pillars extends inside the first stack in the thickness direction. In the second stack, second conductive layers and second insulating layers are alternately stacked in the thickness direction. Each of the plurality of second pillars extends inside the second stack in the thickness direction. The third stack is positioned between the first stack and the second stack in the first direction. In the third stack, third insulating layers and fourth insulating layers including a material different from a material of the third insulating layer are alternately stacked in the thickness direction of the substrate.Type: GrantFiled: August 7, 2020Date of Patent: September 6, 2022Assignee: Kioxia CorporationInventors: Kosei Noda, Go Oike