Abstract: Aspects are directed to systems in which control node communicates through a peripheral-side wired communications bus for data communications with other bus-coupled nodes. The control node acts as a master with a main-circuit domain during an initialization mode and when the main-circuit domain is deactivated, and acts as a slave, after completion of the initialization mode and when the main-circuit domain is not deactivated. An isolation circuit is used to isolate the main-circuit domain from the control node and, while the main-circuit domain is deactivated, to facilitate communications over the peripheral-side wired communications bus between the control node and another node connected to the peripheral-side wired communications bus.

Abstract: Embodiments relate to a billboard circuit that stores context information received from various component circuits in an electronic device. The context information indicates an operating status of the corresponding component circuit, system or shared resources. The stored context information may be retrieved by one or more component circuits when events (e.g., turning on of a component circuit) are detected. By using the billboard circuit, a component circuit may detect changes in the operating status of other components circuits and configure or update its operations even when the changes occurred while the component circuit was asleep or disabled. The billboard circuit may monitor updating of the context information by the component circuit and initiate notification to other components circuits when certain entries of the context information is updated.

Abstract: A semiconductor memory device for a hash solution includes a hashing logic block including a plurality of hashing logics configured to perform a hash function, a memory cell block including a plurality of memory cells, and an input/output (I/O) control structure configured to change a data interface between the hashing logic block and the memory cell block based on a characteristic of the hash function to be performed.

Abstract: In one embodiment, an apparatus includes: a first controller to couple to an interconnect to which a plurality of devices may be coupled, the first controller to communicate first information via the interconnect according to the native communication protocol; a first transceiver to drive the first information onto a first line of the interconnect; a second transceiver to drive a clock signal onto a second line of the interconnect; and a second controller to communicate second information via the interconnect. In an embodiment, the native communication protocol is a single-ended communication protocol and the second controller is to communicate the second information differentially via the interconnect. Other embodiments are described and claimed.

Abstract: Some example computing systems herein include two modules, e.g., drivers. A first can instantiate an interface associated with a service routine, receive, by the service routine, a verification message; and send, in response, a confirmation message via the interface. A second can locate the interface; open a handle to the interface; send the verification message via the handle, the verification message identifying at least an interface type or a version; and receive, via the handle, the confirmation message associated with the verification message. In some examples, the first driver is a Plug and Play driver. In some examples, the first module can receive, by the service routine, a command associated with the interface; determine that the command is a valid command based at least in part on stored command data; and send, via the interface, a response to the command.

Abstract: An upstream facing port device (UFP device) and a downstream facing port device (DFP device) allow a host device and a USB device to conduct SuperSpeed communication via a non-USB compliant extension medium. In some embodiments, the UFP device helps overcome increased latency by generating synthetic packets to be transmitted to the DFP device in order to pre-fetch more data packets from the USB device than requested by the host device. In some embodiments, the DFP device adjusts service interval timing or caches data packets from the host device in order to compensate for the increased latency. In some embodiments, the DFP device transmits a synthetic acknowledgement packet to the UFP device to indicate a larger amount of free buffer space than is present on the USB device to help overcome the increased latency.

Abstract: A data storage device, such as a solid state drives (SSD), includes command completion interrupt coalescing. A controller of the data storage device includes one or more completion queues, each including interrupt coalescing protection logic. The interrupt coalescing protection logic detects that a head pointer or a tail pointer in a completion queue has not changed for a predetermined period of time. When the head and tail pointers have not changed for the predetermined period of time, the controller posts an interrupt to a host device.

Abstract: A memory chip (e.g., DRAM) connecting a SoC and an accelerator chip (e.g., an AI accelerator chip). A system including the memory chip and the accelerator chip. The system can include the SoC. The memory chip can include first memory cells to store and provide computation input data (e.g., AI computation input data) received from the SoC to be used by the accelerator chip as computation input (e.g., AI computation input). The memory chip can include second memory cells to store and provide first computation output data (e.g., AI computation output data) received from the accelerator chip to be retrieved by the SoC or reused by the accelerator chip as computation input. The memory chip can also include third memory cells to store second computation output data (e.g., non-AI computation output data) related to non-AI tasks received from the SoC to be retrieved by the SoC for non-AI tasks.

Abstract: A heterogeneous computing system and a heterogeneous computing method using the system are provided and capable of executing accelerating running of a video algorithm. Furthermore, the heterogeneous computing system decreases the complexity of hardware design and the use of resources by pre-processing and simple operations. Furthermore, the required time for adjusting processes of software and hardware of the heterogeneous computing system can be efficiently decreased.

Abstract: An interface device for a processing unit, allowing a plurality of circuits to be connected to a single input port of the processing unit, capable of acquiring a state value of a circuit of the plurality of circuits, when the circuit is biased, including a plurality, of the same cardinal number, of power sources, each power source being associated with a circuit of the plurality of circuits and capable of biasing same, a switch capable of selectively connecting a single circuit of the plurality of circuits to the associated power source, in such a way as to bias the circuit, and of connecting all of the other circuits to ground, the selection of the biased circuit being controlled by a set of at least one output port of the processing unit.

Abstract: A network switch includes a data bus, a register, an endpoint controller and a direct memory access controller. The endpoint controller is configured to receive a descriptor generated by a device driver of a host system, store the descriptor in the register, and transfer data between a root complex controller of the host system and the data bus. The descriptor identifies an address of a buffer in a memory of the host system. The direct memory access controller is configured to receive the address of the buffer from the endpoint controller or the register and, based on the address and an indication generated by the device driver, independently control transfer of the data between the memory of the host system and a network device connected to the network switch. The direct memory access controller is a receive direct memory access controller or a transmit direct memory access controller.

Abstract: In a non-volatile memory circuit, performance is improved by converting data between a serial format, for transfer on and off of the memory circuit, and a parallel format, for transfer to and from the memory latches used for read and writing data into the memory array of the memory circuit. The memory array is split into M+N divisions, but transferred with a degree of parallelism of M, allowing M words of data to be transferred in parallel at a fixed transfer rate while allowing for up to N bad columns in a transfer. In the write path, a column skipping mechanism is used when converting words of write data into a parallel format. In the read path, a set of (M+N) to 1 multiplexers is used to align the word of read data so that read data can be transferred at a fixed rate and without any added latency.

Abstract: A data processing system is implemented with a backup PCI Express system, which is able to take over as the primary PCI Express system for ensuring that an endpoint device continues to function in a desired manner when a root complex in the primary PCI Express system is no longer functioning correctly or is deactivated for maintenance. The endpoint device is coupled to the primary root complex and a backup root complex through a multiplexer. When a failure or shutdown of the primary root complex is detected, the multiplexer is signaled to switch the communication of data from occurring between the primary root complex and the endpoint device to then occur between the backup root complex and the endpoint device. A PCI Express Link may be utilized to communicate such a failure or shutdown and/or to transfer information from the primary PCI Express system to the backup PCI Express system when the switch occurs.

Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

Abstract: In one embodiment, an apparatus includes: a processing circuit to execute instructions; and a host controller coupled to the processing circuit to perform a key exchange with a second device to couple to the apparatus via a bus to which a plurality of devices may be coupled, and in response to a successful completion of the key exchange, enable secure communication with the second device. Other embodiments are described and claimed.

Abstract: A DRP determining method is provided. The method includes the following steps. Firstly, a first DRP electronic device and a second DRP electronic device are connected by a USB Type-C line. Then, the first DRP electronic device is set to one of a host and a device. Then, the second DRP electronic device is set to one of the host and the device. When the connection between the first DRP electronic device and the second DRP electronic device is disconnected and then re-connected, at least one of the first DRP electronic device and the second DRP electronic device is set to the other one of the host and the device.

Abstract: An apparatus and method are described, the apparatus comprising processing circuitry to perform data processing operations, microarchitecture circuitry used by the processing circuitry during performance of the data processing operations, and an interface to receive interrupt requests. The processing circuitry is responsive to a received interrupt request to perform an interrupt service routine, and the apparatus comprises prediction circuitry to determine a predicted time of reception of a next interrupt of at least one given type. The apparatus also comprises microarchitecture control circuitry arranged to vary a configuration of the microarchitecture circuitry between a performance based configuration and a responsiveness based configuration in dependence on the predicted time, so as to seek to increase the responsiveness of the apparatus to interrupts as the predicted time is approached.

Abstract: A communication system comprising: a digital serial bus, and a master device and at least one slave device connected to the bus. The master and the slave(s) are adapted to communicate according to a predefined communication protocol. The master is adapted for transmitting a continuous bitstream in the form of a plurality of frames, such that each frame comprises one or more words. Each word has a constant time duration, with the first word of each frame being a unique word transmitted by the master for indicating the start of a frame. One or more bits each word is transmitted by the master as a dominant bit; a non-dominant bit, for allowing the at least one slave to overwrite. The at least one slave is adapted for overwriting in the continuous bitstream some non-dominant bits to transmit data in a quasi-synchronous manner.

Abstract: A system and method for providing efficient communication between a processor and a device. An interposer is provided to send signals from the processor to the device. The interposer includes a printed circuit board, a first interconnection port communicating with the processor, and a second interconnection port communicating with the device. A retimer/redriver circuit is coupled to the first interconnection port and the second interconnection port, and the retimer/redriver circuit routes signals from the first interconnection port to the second interconnection port.

Abstract: An apparatus includes a processor and a machine-readable medium coupled to the processor and comprising instructions. The instructions, when loaded into the processor and executed, configure the processor to identify that a USB element has attached to a USB hub at a port, classify the USB element according to power operations of the USB element, and assign an upstream or downstream setting of the port based upon the classification of the USB element based on power operations of the USB element. The instructions may further configure the processor to classify the USB element as only a producer of power, evaluate whether an enumeration process is initiated within a timeout period, and if so, assign the USB element as a USB host.