Patents Examined by Kimberly Trice
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Patent number: 7879691Abstract: Exemplary embodiments provide methods and systems for assembling electronic devices, such as integrated circuit (IC) chips, using a release member having a phase change material. Specifically, IC elements/components can be selectively received, stored, inspected, repaired, and/or released in a scalable manner during the assembly of IC chips by inducing phase change of the phase change material. The release member can be flexible or rigid. In some embodiments, the release member can be used for a low cost placement of the IC elements in combination with an SOI (silicon on insulator) wafer and/or an intermediate transfer member. In other embodiments, the release member can be used for a low cost placement of the IC elements in combination with a release wafer.Type: GrantFiled: September 24, 2008Date of Patent: February 1, 2011Assignee: Eastman Kodak CompanyInventors: Roger S. Kerr, Timothy J. Tredwell, Seung-Ho Baek
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Patent number: 7851800Abstract: A TFT and an OLED device are provided. The TFT includes a substrate, a gate, a gate insulator, a source/drain layer, an isolated layer, and a channel layer. The gate is disposed on the substrate. The gate insulator is disposed on the substrate and covers the gate. The source/drain layer is disposed on the gate insulator, and exposes a portion of the gate insulator above the gate. The isolated layer is disposed on the source/drain layer and has an opening to expose a portion of the gate insulator and a portion of the source/drain layer above the gate. The channel layer is disposed in the opening of the isolated layer. Further, the channel layer is exposed by the opening and is electrically connected to the source/drain layer. On the other hand, the OLED device mainly includes a driving circuit and an organic electro-luminescent unit.Type: GrantFiled: December 30, 2008Date of Patent: December 14, 2010Assignee: Industrial Technology Research InstituteInventors: Tarng-Shiang Hu, Yi-Kai Wang, Jing-Yi Yan, Tsung-Hsien Lin, Jia-Chong Ho
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Patent number: 7842962Abstract: A P-type electrode material is provided on a top surface of a P-type contact layer. The P-type electrode material is formed with an AuGa film, an Au film, a Pt film, and an Au film. The AuGa film is provided on the P-type contact layer. The Au film is provided on the AuGa film. The Pt film is provided on the Au film. The Au film is provided on the Pt film. With this, a nitride semiconductor device having a P-type electrode which can decrease a contact resistance between a P-type contact layer and the P-type electrode is obtained.Type: GrantFiled: November 16, 2005Date of Patent: November 30, 2010Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuomi Shiozawa, Toshiyuki Oishi, Kazushige Kawasaki, Yuji Abe
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Patent number: 7820483Abstract: A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips.Type: GrantFiled: February 2, 2007Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Luc Belanger, David Danovitch, John U. Knickerbocker
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Patent number: 7816174Abstract: A control element of an organic electro-luminescent display includes a first transistor, a second transistor and a capacitor. The first gate electrode of the first transistor is electrically connected to a scan line, and the first source/drain electrode of the first transistor is electrically connected to a data line. The second gate electrode of the second transistor is electrically connected to the second source/drain electrode of the first transistor. The third source/drain electrode of the second transistor is electrically connected to a working voltage, and the fourth source/drain electrode of the second transistor is electrically connected to a light emitting diode. One end of the capacitor is electrically connected to the second gate electrode. The material of the dielectric layer of the capacitor is different from the material of the gate dielectric of one of the first transistor and the second transistor.Type: GrantFiled: August 18, 2009Date of Patent: October 19, 2010Assignee: Au Optronics CorporationInventors: Jen-Chien Peng, Meng-Hsiang Chang
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Patent number: 7808095Abstract: There is provided an ultra slim semiconductor package comprising: a multilayer thin film layer including at least one or more dielectric layers and at least one or more redistribution layers; at least one semiconductor chip electrically connected to the redistribution layer and mounted on the multilayer thin film layer; conductive structures electrically connected to the redistribution layer and each formed in a post shape at one side of the multilayer thin film layer; a molding part formed on the multilayer thin film layer and at least partially covering the conductive structures and the semiconductor chip; and bumps for external connection formed on the molding part and electrically connected to the conductive structures. The semiconductor package according to the present invention enables mass production at wafer level, is easily stacked between the packages, and has an excellent electrical characteristic.Type: GrantFiled: January 31, 2008Date of Patent: October 5, 2010Assignee: Nepes CorporationInventor: Gi-Jo Jung
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Patent number: 7799593Abstract: The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer. Next, the substrate is etched to form a plurality of concave zones and a plurality of convex zones with the chemical reaction layer overhead. Next, the chemical reaction layer is removed to form an irregular geometry of the concave zones and convex zones on the surface of the substrate. Then, a semiconductor light emitting structure is epitaxially formed on the surface of the substrate. Thereby, the present invention can achieve a light emitting diode structure having improved internal and external quantum efficiencies.Type: GrantFiled: August 10, 2009Date of Patent: September 21, 2010Assignee: Tekcore Co., Ltd.Inventors: Chia-Ming Lee, Hung-Cheng Lin, Jen-Inn Chyi
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Patent number: 7786592Abstract: A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.Type: GrantFiled: January 10, 2006Date of Patent: August 31, 2010Inventor: John Trezza
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Patent number: 7772031Abstract: The semiconductor apparatus includes a semiconductor chip, and a source electrode and a gate electrode which are formed on the semiconductor chip and electrically connected with a lead frame. The source electrode is electrically connected with the lead frame by being laser-welded with a thin-film shaped connecting portion formed at an end of the lead frame. This enables the provision of a semiconductor apparatus with enhanced productivity and yields which exhibits high electrical operability and reliability.Type: GrantFiled: January 8, 2007Date of Patent: August 10, 2010Assignee: NEC Electronics CorporationInventors: Takekazu Tanaka, Kouhei Takahashi
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Patent number: 7745303Abstract: The present invention provides a method of manufacturing a trench with a rounded corner portion and a broadened opening. Anisotropic oxidation is carried out using a halogen oxidation method using dichloroethylene (DCE) to form an anisotropic oxide film such that the film thickness in a shoulder portion of the trench is thick and gradually decreases nearer the bottom, the anisotropic oxide film is removed, and the shoulder portion of the trench is preferentially backed off, thereby rounding the shoulder portion sufficiently to broaden the opening. Then, an insulating member is embedded in the trench. The rounded portion of the shoulder portion of the trench and vicinity thereof is used as a channel of a MOS transistor.Type: GrantFiled: July 26, 2006Date of Patent: June 29, 2010Assignee: Elpida Memory Inc.Inventor: Hirohisa Yamamoto
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Patent number: 7741212Abstract: A semiconductor device and method for manufacturing the same are provided, capable of narrowing feature size by utilizing the property of oxidation of a material. In one method, a polysilicon layer can be patterned into a fine pattern up to a critical dimension using a photolithography process. Then the patterned polysilicon layer can be oxidized, thereby narrowing the gap between adjacent polysilicon patterns and narrowing the polysilicon patterns through the oxidation process. The narrowed polysilicon patterns and/or the narrowed gap between adjacent polysilicon patterns can be used to form vias or trenches in the substrate (or layer) below the polysilicon layer having a width narrower than the critical dimension.Type: GrantFiled: August 16, 2007Date of Patent: June 22, 2010Assignee: Dongbu Hitek Co., Ltd.Inventor: Eun Soo Jeong
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Patent number: 7741163Abstract: A method of fabricating a thin film transistor is provided. A gate is formed on a substrate. A gate insulator is formed on the substrate to cover the gate. A source/drain layer is formed on the gate insulator, and a portion of the gate insulator above the gate is exposed by the source/drain layer. An isolated layer is formed on the source/drain layer and has an opening to expose a portion of the gate insulator and a portion of the source/drain layer above the gate. A channel layer is formed in the opening of the isolated layer to be electrically connected to the source/drain layer, and the channel layer is exposed by the opening.Type: GrantFiled: September 19, 2006Date of Patent: June 22, 2010Assignee: Industrial Technology Research InstituteInventors: Tarng-Shiang Hu, Yi-Kai Wang, Jing-Yi Yan, Tsung-Hsien Lin, Jia-Chong Ho
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Patent number: 7737560Abstract: A power semiconductor IC device is disclosed. In one embodiment, the device includes a substrate, and a layer structure formed on the substrate. The layer structure includes a metallization layer including copper, wherein the metallization layer is formed as a stack structure including at least two copper layers and a stabilization layer between the two copper layers.Type: GrantFiled: May 18, 2006Date of Patent: June 15, 2010Assignee: Infineon Technologies Austria AGInventors: Matthias Stecher, Renate Hofmann, Joerg Busch
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Patent number: 7728408Abstract: A vertical BJT which has a maximal current gain for a photodiode area. According to embodiments, since the BJT can be formed together with the photodiode, and collector current flows up and down based on the double base structure, the magnitude of the current may be increased.Type: GrantFiled: August 20, 2007Date of Patent: June 1, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Su Lim
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Patent number: 7727848Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.Type: GrantFiled: July 9, 2008Date of Patent: June 1, 2010Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, David Vaclav Horak, Charles William Koburger, III, Jack Allan Mandelman, William Robert Tonti
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Patent number: 7723240Abstract: A method for forming a dielectric is provided. The method includes providing a substrate having a silicon-containing semiconductor layer within a process chamber. The process chamber is capable of ionizing a process precursor to a plasma comprising an oxygen-containing element and a fluorocarbon-containing element. A surface portion of the silicon-containing material is oxidized by using the plasma to convert the surface portion into an oxidized dielectric material.Type: GrantFiled: May 15, 2008Date of Patent: May 25, 2010Assignee: Macronix International Co., Ltd.Inventors: Shih-Ping Hong, Han-Hui Hsu
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Patent number: 7719081Abstract: In a semiconductor device of the present invention, an epitaxial layer is formed on a P type single crystal silicon substrate. Isolation regions are formed in the epitaxial layer, and are divided into a plurality of element formation regions. An NPN transistor is formed in one of the element formation regions. An N type diffusion layer is formed between a P type isolation region and a P type diffusion layer which is used as a base region of the NPN transistor. This structure makes the base region and the isolation region tend not to be short-circuited. Hence, the breakdown voltage characteristics of the NPN transistor can be improved.Type: GrantFiled: December 8, 2006Date of Patent: May 18, 2010Assignee: Sanyo Electric Co., Ltd.Inventors: Mitsuru Soma, Hirotsugu Hata, Minoru Akaishi
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Patent number: 7709350Abstract: A method for manufacturing a semiconductor elemental device including an SOI structure in which an SOI layer is laminated, includes the steps of setting transistor forming regions and a device isolation region to the SOI layer, forming a pad oxide film over the SOI layer and forming an oxidation-resistant film over the pad oxide film; forming a resist mask in a region corresponding to each of the transistor forming regions, and etching the oxidation-resistant film and the pad oxide film with the resist mask as a mask to expose the SOI layer of the device isolation region; removing the resist mask and oxidizing the exposed SOI layer by a LOCOS method using the oxidation-resistant film to form a field oxide film; and implanting amorphization ions in an edge portion formed in the SOI layer upon formation of the field oxide film to amorphize the edge portion.Type: GrantFiled: January 23, 2006Date of Patent: May 4, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Hirotaka Komatsubara
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Patent number: 7704850Abstract: A semiconductor device for determining an overlay error on a semiconductor substrate includes a first and a second transistor. Each transistor includes two diffusion regions associated with a gate, the diffusion regions of each transistor being arranged in a first direction. The second transistor is arranged adjacent to the first transistor in a second direction perpendicular to the first direction. The first and second gate each have a non-uniform shape, and the second gate is oriented with respect to an orientation of the first gate in such a way that an effect of an overlay error on a device parameter of the second transistor has an opposite sign in comparison to an effect of the overlay error on a corresponding device parameter of the first transistor.Type: GrantFiled: September 8, 2006Date of Patent: April 27, 2010Assignee: ASML Netherlands B.V.Inventors: Mircea Dusa, Axel Nackaerts, Gustaaf Verhaegen
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Patent number: 7692308Abstract: The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures.Type: GrantFiled: October 23, 2008Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Matthew E. Colburn, Louis C. Hsu, Wai-Kin Li