Abstract: The MEMS Sensor Suite on a Chip provides the capability, monolithically integrated onto one MEMS chip, to sense temperature, humidity, and two axes of acceleration. The device incorporates a MEMS accelerometer, a MEMS humidity sensor, and a MEMS temperature sensor on one chip. These individual devices incorporate proof masses, suspensions, humidity sensitive capacitors, and temperature sensitive resistors (thermistors) all fabricated in a common fabrication process that allows them to be integrated onto one micromachined chip. The device can be fabricated in a simple micromachining process that allows its size to be miniaturized for embedded and portable applications. During operation, the sensor suite chip monitors temperature levels, humidity levels, and acceleration levels in two axes. External circuitry allows sensor readout, range selection, and signal processing.

Abstract: The present invention relates to a method of manufacturing a vertical GaN-based LED. The method includes forming an insulating pattern on a substrate to define LED regions having a predetermined size; sequentially stacking an n-type GaN-based semiconductor layer, an active layer, and a p-type GaN-based semiconductor layer on the substrate except for the insulating pattern to form a light emitting structure; removing the insulating pattern to divide the light emitting structure into LED sections having a predetermined size; forming p-electrodes on the LED sections, respectively; forming a structure support layer on the p-electrodes; removing the substrate to expose the divided n-type GaN-based semiconductor layer; and forming n-electrodes on the exposed n-type GaN-based semiconductor layer.

Abstract: A method of manufacturing a thin film transistor (TFT) substrate to minimize a rugged surface of an organic layer overlapping with a storage electrode is provided. The method includes forming a passivation layer on a substrate having a storage electrode and an organic layer covering the passivation layer, forming a concave portion by partially removing a portion of the organic layer that overlaps with the storage electrode, planarizing a rugged pattern located on the bottom of the concave portion, and forming an opening extending to a surface of the passivation layer by removing the planarized organic layer from the concave portion.

Abstract: A method of fabricating a through via connection useful in providing a vertical wafer-to-wafer interconnect structure is provided as well as the vertical interconnect structure that is formed by this method. The method of the present invention using only a metal stud for the vertical connection therefore no alpha radiation is generated by the metal stud. The method of the present invention includes an inserting step, a heating step, a thinning step and backside processing.