Abstract: After an element isolation region is formed using a field-forming silicon nitride film, the silicon nitride film and a semiconductor substrate are patterned. Thereafter, the silicon nitride film and the semiconductor substrate are patterned, thereby forming a gate trench reaching the semiconductor substrate in an active region. Next, after a gate electrode is formed within a gate trench, the silicon nitride film is removed, thereby forming a contact hole. A contact plug is buried into this contact hole. Accordingly, a diffusion layer contact pattern becomes unnecessary, and the active region can be reduced. Because a gate electrode is buried in the gate trench, a gate length is increased, and a sub-threshold current can be reduced.

Abstract: A memory device is disclosed. A pillar structure comprises a first electrode layer, a dielectric layer overlying the first electrode layer, and a second electrode layer overlying the dielectric layer. A phase change layer covers a surrounding of the pillar structure. A bottom electrode electrically connects the first electrode layer of the pillar structure. A top electrode electrically connects the second electrode layer of the pillar structure.

Abstract: The present invention is a front-side contact, back-side illuminated (FSC-BSL) photodiode arrays and front-side illuminated, back-side contact (FSL-BSC) photodiode arrays having improved characteristics, including high production throughput, low-cost manufacturing via implementation of batch processing techniques; uniform, as well as high, photocurrent density owing to presence of a large continuous homogeneous, heavily doped layer; and back to front intrachip connections via the homogenous, heavily doped layers on the front and back sides of the substrate.

Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.

Abstract: An electrical fuse and a method for forming the same are provided. The electrical fuse includes a dielectric layer over a shallow trench isolation region and a contact plug extending from a top surface of the dielectric layer to the shallow trench isolation region, wherein the contact plug comprises a middle portion substantially narrower than the two end portions. The contact plug forms a fuse element. The electrical fuse further includes two metal lines in a metallization layer on the dielectric layer, wherein each of the two metal lines is connected to different ones of the end portions of the contact plug.

Abstract: A CMOS image sensor and a fabricating method thereof are provided. The method includes forming a nitride layer over a boundary region between a device isolation region and a pixel region, forming a silicide barrier layer in the pixel region and performing a silicide process. A boundary portion of the silicide barrier layer formed in the pixel region can be prevented from being wet-etched while the silicide barrier layer is removed by the wet etching process.

Abstract: A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate: a first layer below and second layers on a gate with spacers, source and drain regions adjacent to the gate, silicides on the gate and source and drain regions; disposing a stress layer over the structure resulting from the forming step; disposing an insulating layer over the stress layer; removing portions of the insulating layer to expose a top surface of the stress layer; removing the top surface and other portions of the stress layer and portions of the spacers to form a trench, and then disposing a suitable stress material into the trench.

Abstract: An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.

Abstract: A memory device includes a substrate, a first gate stack overlying the substrate, a second gate stack overlying the substrate and spaced apart from the first gate stack, an oxide region formed at a first depth within the substrate and between the first and second gate stacks, and an impurity doped region formed at a second depth within the substrate and between the first and second gate stacks, the first depth being lower than the second depth.

Abstract: Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the first well and having a gate insulating film of a first thickness, and a second transistor formed in the second well and having a gate insulating film of a second thickness less than the first thickness. The first well has a first impurity concentration distribution having an extremum maximum value only at the depth equal to or greater than the first depth. The second well has a second impurity concentration distribution which is superposition of the first impurity concentration distribution, and another impurity concentration distribution which shows an extremum maximum value at a second depth less than the first depth, the superposition shows also an extremum maximum value at the second depth.

Abstract: The invention provides a method of manufacturing a flash memory device. Nitride film spacers are formed on sidewalls of protruded isolation films. A recess is formed in a semiconductor substrate by a self-aligned etch process using the nitride film spacers as masks. It is therefore possible to form a uniform recess over the entire wafer. Furthermore, a floating gate is formed on the semiconductor substrate including the recess in a self-aligned manner. Accordingly, a contact area between the floating gate and the semiconductor substrate can be increased as large as a recess surface area.

Abstract: The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer. Next, the substrate is etched to form a plurality of concave zones and a plurality of convex zones with the chemical reaction layer overhead. Next, the chemical reaction layer is removed to form an irregular geometry of the concave zones and convex zones on the surface of the substrate. Then, a semiconductor light emitting structure is epitaxially formed on the surface of the substrate. Thereby, the present invention can achieve a light emitting diode structure having improved internal and external quantum efficiencies.

Abstract: A control element of an organic electro-luminescent display includes a first transistor, a second transistor and a capacitor. The first gate electrode of the first transistor is electrically connected to a scan line, and the first source/drain electrode of the first transistor is electrically connected to a data line. The second gate electrode of the second transistor is electrically connected to the second source/drain electrode of the first transistor. The third source/drain electrode of the second transistor is electrically connected to a working voltage, and the fourth source/drain electrode of the second transistor is electrically connected to a light emitting diode. One end of the capacitor is electrically connected to the second gate electrode. The material of the dielectric layer of the capacitor is different from the material of the gate dielectric of one of the first transistor and the second transistor.

Abstract: Method for the light emitting diode (LED) having the nanorods-like structure is provided. The LED employs the nanorods are subsequently formed in a longitudinal direction by the etching method and the PEC method. In addition, the plurality of the nanorods is arranged in an array so that provide the LED having much greater brightness and higher light emission efficiency than the conventional LED.

Abstract: A conducting layer in a chip package module includes one or a plurality of through hole penetrating the top of a base being disposed at the bottom of an insulating layer in the chip package module, and inner wall of the through hole being applied with insulation material so that the conductive layer subsequently constructed to the peripheral of the insulation layer may pass the through hole to extend to where above the base before construction of a masking layer and multiple circuit pins to complete construction of the conducting layer that is totally enveloped so to prevent easy oxidization at the conducting layer and improve stability of the chip package to avoid breaking up due to external force applied.

Abstract: Disclosed is a method for forming a via-hole for interconnection of metallization and/or metal wires in a semiconductor device. The present method may include the steps of: (a) forming an insulating layer on a semiconductor substrate including a lower metallization and/or metal wiring; (b) forming a mask (e.g., a photo-resist pattern) on the insulating layer; (c) dry etching the insulating layer using the photo-resist pattern as a mask to form a via-hole in the insulating layer; and (d) in the same dry etching chamber, etching a top portion of the insulating layer in the vicinity of the via-hole with an etchant comprising oxygen and argon.

Abstract: An electronic device can include a semiconductor fin with a first gate electrode adjacent to a first wall, and a second gate electrode adjacent to a second wall. In one embodiment, a conductive member can be formed overlying the semiconductor fin, and a portion of the conductive member can be reacted to form the first and second gate electrodes. In another embodiment, a patterned masking layer can be formed including a masking member over a gate electrode layer, and portion of the masking member overlying the semiconductor fin can be removed. In still another embodiment, a first fin-type transistor structure can include the semiconductor fin, the first and second gate electrodes, and a first insulating cap. The electronic device can also include a second fin-type transistor structure having a second insulating cap thicker than the first insulating cap.

Abstract: A method for manufacturing an LCOS device includes forming an interlayer dielectric layer overlying a surface region of a substrate. The interlayer dielectric layer is patterned to form a plurality of recessed regions. Each of the recessed regions corresponds to a pixel element for a LCOS device and is isolated by a portion of dielectric material defining a border for each of the recessed regions. An aluminum material or aluminum alloy material is deposited within each of the recessed regions. A photomask is formed overlying the aluminum material and patterned to expose the recessed regions while protecting the border regions. Exposed regions of the aluminum material is removed while the border regions with the photomask is protected. The method continues the removing until the aluminum material has been removed to a vicinity of an upper region of the border regions. The patterned photomask is stripped to expose protruding aluminum material.

Abstract: A method for fabricating an LCD device includes forming sequentially a first conductive layer, a first insulation layer, a semiconductor layer, and an ohmic contact layer on a first substrate; forming a gate line by patterning the first conductive layer, the first insulation layer, the semiconductor layer, and the ohmic contact layer; exposing a first gate pad electrode connected with the gate line; insulating the gate line; forming a data line that intersects the gate line, wherein an electrode part is formed extending from the data line such that the electrode part is formed over the semiconductor layer and the ohmic layer, and defines an active pattern; forming a transparent electrode layer on the substrate including the electrode part; and forming source, drain, and pixel electrodes simultaneously by patterning at least one of the transparent electrode layer, the electrode part, and the ohmic contact layer.

Abstract: An image sensor and a method for manufacturing the same are provided. The image sensor comprises a pixel region defined on a substrate, an interlayer dielectric on the substrate and comprising a trench above the pixel region, a color filter within the trench, and a microlens on the color filter.