Abstract: An operational amplifier is provided including first and second conduction types of differential amplifier circuits, an output circuit for outputting an output signal by first and second driver transistors of the first and the second conduction types. The differential amplifier circuits of the first and the second conduction types include first and second differential pairs of transistors of the first and the second conduction types to which an input signal and the output signal are respectively input. When the transistor of a p-type is in an off-state, a first auxiliary circuit subsidiarily drives a first output node (a first inverted output node). When the transistor of an n-type is in an off-state, a second auxiliary circuit subsidiarily drives a second output node (a second inverted output node).

Abstract: A digital TV receiver includes an A/D converter for converting an analog signal into a digital signal, a carrier recovery for converting the digital passband signal into a digital baseband signal, and a symbol clock recovery for converting digital baseband real/imaginary component signals into OQAM type of real/imaginary component signals, detecting timing error information by high-passband-filtering, squaring, and adding the OQAM real/imaginary signals, and for generating and outputting the at least two times the frequency of the symbol clock corrected from the detected timing error information.

Abstract: A power amplifier for use in a mobile handset includes an amplifying transistor, a bias circuit including a bias transistor, the bias circuit providing a bias current to bias the amplifying transistor, and a bias current control circuit, responsive to fluctuation in a reference voltage and variation in temperature, for adjusting the bias current to control an operation current of the amplifying transistor.

Abstract: A device of digital TV receiver including an A/D converter for converting an analog signal into a digital passband signal, a carrier recovery for converting the digital passband signal into a digital baseband signal, and a symbol clock recovery for calculating the digital passband real/imaginary signals of the A/D converter or the digital baseband real/imaginary signals of the carrier recovery, detecting timing error information, and generating and outputting two times the frequency of the symbol clock recovered from the detected timing error information is disclosed.

Abstract: A power device(s) is biased and operates in Class-AB. Crossover distortion is minimized over a broad range of operating conditions, not only for a nominal case. The bias current of a power transistor is automatically adjusted in response to process and temperature variations. Preferably, the adjustment is performed using an error-feedback arrangement. An exemplary ‘rule’ for bias adjustment involves satisfying a proportionality relationship between the small-signal device transconductance at the operating point, and a maximum device transconductance. A dual replica master-slave control architecture is utilized. A self-adapting circuit is provided to change the bias current (or voltage) so that the value is always the optimum value, irrespective of operating temperature and/or process variations. Self-biasing is introduced wherein no manual adjustment is necessary. A stable amplifier is formed having great robustness to process and temperature variations.

Abstract: A device of digital TV receiver includes an A/D converter for converting an analog passband signal into a digital passband signal, a carrier recovery for converting the digital passband signal into a digital baseband signal, and a symbol clock recovery for calculating the digital passband real/imaginary signals of the A/D converter or the digital baseband real/imaginary signals of the carrier recovery and squaring the calculated result, detecting timing error information, and generating and outputting two times the frequency of a symbol clock recovered from the detected timing error information.

Abstract: Systems and methods for reducing the noise level in a multi-channel digital audio system by staggering the timing of the pulse-width modulation in the different channels and thereby reducing the magnitude and increasing the frequency characteristics of the generated switching noise. One embodiment comprises a multi-channel digital PWM amplifier in which the timing signals used by each channel's modulator are staggered to evenly space the switching edges of the generated PWM signals. An additional, complementary delay is implemented in each of the channels to equalize the total delay for each channel so that the outputs of the channels are synchronized. The different channels may be implemented on different chips, in which case the chips may be synchronized prior to staggering the signals processed in each of the channels.

Abstract: A transceiver for a serial data bus is provided which transceiver includes error management. In a first example embodiment of a transceiver, error management is provided which supplies an error signal when the data bus lines are active and the receiving line simultaneously is inactive. In a second example embodiment of a transceiver, error management is provided which triggers an error signal when the transmission line is active for a longer period than a predetermined time interval, which error signal is cancelled when both the transmission line is inactive and the receiving line is active.

Abstract: A Viterbi decoder includes a number of classical Add-Compare-Select units and a number of further Add-Compare-Select unit having a lower complexity butterfly unit (300) having only two adder means, such that the further Add-Compare-Select unit has a butterfly unit (300) comprising: first adder means (310) for receiving a first path metric and a branch metric and for producing at its output the addition thereof; and second adder means (320) for receiving a second path metric and said branch metric and for producing at its output the addition thereof. First comparator means (330) are coupled to receive the output of the second adder means and coupled to receive the first path metric for comparing therebetween. Second comparator means (340) are coupled to receive the output of the first adder means and coupled to receive the second path metric for comparing therebetween.

Abstract: A transmission signal and a pilot signal are predistorted by a digital predistorter 13 by use of a power-series model, and the predistorted output is converted by a digital-analog converter 14 to an analog signal. The analog signal is up converted by a frequency converter 15 to an RF-band signal, which is transmitted after being power-amplified by a Doherty amplifier 16. The pilot signal is extracted by a pilot signal extractor 17 from the output from the Doherty amplifier, and the extracted pilot signal is down converted by a frequency converter 18 to a baseband signal. The baseband pilot signal is converted by an analog-digital converter 19 to a digital pilot signal. A control part 21 detects an odd-order distortion component from the digital pilot signal, and based on the detected result, controls parameters of the digital predistorter.

Abstract: There is disclosed a method of allocating a channelisation code comprising, for each user, defining a path in the code tree based on a required range of spreading factors, selecting a node of the path in dependence on the currently required spreading factor; and reserving all nodes on the code tree in an upward and downward direction from the selected node, wherein the selected node for any user must not coincide with a node reserved by any other user.

Abstract: A signal detection circuit for receiving a digital baseband signal comprising an amplitude modulated symbol stream of Logic 0 symbols and Logic 1 symbols, each of the Logic 0 and Logic 1 symbols comprising S sequential samples, wherein the amplitude modulated symbol stream contains a preamble of N known symbols preceding a plurality of user data symbols. The signal detection circuit comprises: A) a signal mean determination circuit that receives G samples from the digital baseband signal and determines an amplitude mean value associated with the amplitude modulated symbol stream; and B) a correlation circuit that detects the preamble.

Abstract: The present invention utilizes circuitry, already present in receivers, to calibrate and correct for gain and phase errors in a transceiver device. The present invention employs a digital signal processor along with multiple phase shifters and all pass networks to ensure proper levels of quadrature signals within the transceiver. An internally generated double sideband suppressed carrier signal is created to produce the calibration signals used by the digital signal processor.

Abstract: A method for reducing the crest factor of a multi-carrier signal includes evaluating an inverse Fourier transform of the multi-carrier signal, thereby generating a transformed multi-carrier signal; defining a signal-to-be-corrected to be the transformed multi-carrier signal; generating a simulated output signal; estimating a signal maximum of the simulated output signal; deriving a first correction variable on the basis of the estimate; correcting the signal-to-be-corrected using at least the first correction variable, thereby generating a corrected output signal having a reduced crest factor; defining the corrected output signal to be the signal-to-be-corrected; and iteratively repeating the last five steps until the corrected output signal has a crest factor below a predetermined threshold, or a predetermined number of iterations has occurred.

Abstract: Systems and methods for automatically adjusting the alignment of high-side and low-side pulse width modulated signals to improve dead time and shoot-through conditions. In one embodiment, a system includes a digital amplifier controller, an amplifier output stage coupled to the controller and configured to receive audio signals from the controller, and one or more sensors coupled to the output stage. The sensors are configured to detect and/or measure various parameters, such as shoot-through current and distortion, which are associated with the operation of the output stage. The sensors provide feedback to an internal processor or modulator of the controller, which then adjusts the timing of the high-side and low-side signals to improve the operating conditions of the output stage by minimizing shoot-through current and/or distortion.

Abstract: A low noise amplifier (LNA) operates over multiple frequency bands while occupying less silicon area than known LNA implementations. The LNA includes output matching that can be tuned by an adjustable inductor together with a tunable capacitor bank.

Abstract: A transmitting apparatus and method may inverse Fourier transform transmit data converted to parallel form to obtain a first signal. The band of a second signal is limited to a guard frequency band adjacent to the band of the first signal, and a signal comprising the first and second signals is transmitted.