Abstract: A LOC leadframe-based semiconductor package includes a chip with multiple rows of bonding pads. At least a bus bar is attached to the chip and is disposed between a first row of bonding pads and the fingers of the leads. A plurality of bonding wires electrically connect the first row of bonding pads to the fingers of the leads. The portion of the bus bar attached to the active surface of the chip includes a bent section bent away from the fingers. A long bonding wire electrically connects one of a second row of bonding pads to one of the fingers of the leads by overpassing the bent section. Therefore, the distance between the long bonding wire and the bus bar is increased to avoid electrical short between the long bonding wire and the bus bar and to enhance the quality of electrical connections of the LOC semiconductor package.

Abstract: Chips are stacked and mounted on a circuit board having external connection electrodes and mounted thereon by wire bonding. At least one of the chips stacked on the chip includes overhung portions each of which has a start point inside bonding pads, is made thinner in a direction towards the outer periphery to an end point reaching the side wall and forms a space used to accommodate ball bonding portions between the overhung portion and the main surface of the chip arranged in the lower stage on a backside corresponding in position to the bonding pads, and insulating members formed to cover the overhung portions and prevent bonding wires of the chip arranged in the lower stage from being brought into contact with the upper-stage chip.

Abstract: A heat sink apparatus having a plurality of chips attached to a first surface of a flexible carrier and a plurality of heat sink fins. One or more additional chips may be attached to a second surface of the flexible carrier. The flexible carrier has at least one complementary fold, the complementary fold having a counterclockwise fold and a clockwise fold as seen from the side. A first chip back surface of a first chip and a second chip back surface of a second chip are in thermal contact with a particular heat sink fin, that is, sharing the same heat sink fin. Thermal contact between the chips and heat sink fins is effected by force, by thermally conducting adhesive, by thermal grease, or by a combination of force and/or thermally conducting adhesive and/or thermal grease.

Abstract: A punch type substrate strip includes a plurality of substrate units, a plurality of slots and at least one plating-trace collecting hole. The slots are formed around the substrate units. The plating-trace collecting hole is located outside the substrate units. The substrate strip is provided with a plurality of connecting pads, a plurality of first plating traces and at least one second plating trace. The connecting pads are disposed in each substrate unit, and the first plating traces and the second plating trace are electrically connected to the connecting pads. The first plating traces have a plurality of first broken ends located in the slots. The second plating trace is extended across a region located between the slots, and has a second broken end located in the plating-trace collecting hole. Accordingly, more extensive space for plating traces can be provided.

Abstract: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, which is provided with a stepped surface positioned at lower level at a portion of the base plate than a main surface of the base plate. A first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed on the first and the second dielectric plate. An insulator is mounted on the stepped surface of the base plate, which forms a part of the sidewall. Power supply portions are provided including a band-shaped conductor. An interconnection is provided which connects the band-shaped conductor to the circuit pattern.

Abstract: A semiconductor integrated circuit having a multilayer wiring structure is provided which includes: a top metal wiring layer (MTOP) including a plurality of top layer power supply wirings and a next-to-top metal wiring layer (MTOP-1) directly below the top metal wiring layer MTOP including a plurality of next-to-top layer power supply wirings. Each of the top layer and the next-to-top layer power supply wirings also includes first potential wirings for supplying a first potential to the circuit elements and second potential wirings for supplying a second potential to the circuit elements. The top layer power supply wirings and the next-to-top layer power supply wirings cross each other and have a top layer insulating film disposed between them. First and second contacts are provided in the insulating film for connecting the first potential wirings and second potential wirings in the top and the next-to-top metal wiring layers with each other.

Abstract: A lead frame (200) for housing an integrated circuit is disclosed comprising a main member (220) and an engagement portion (230) for receiving an integrated circuit (210). The integrated circuit (210) is located at the engagement portion (230) and engaged with the lead frame through resilient engagement with the first and second engagement members (222, 223). The first and second engagement members (222,223) which depend from the main member, secure the integrated to the lead frame by engaging in resilient contact respective opposed surfaces of the integrated circuit. The integrated circuit is engaged to the lead frame by clipping into it into position between the engagement members. There is no need for a gluing process unlike conventional lead frame designs which where the integrated circuit is attached to a lead frame by gluing it onto the die paddle.

Abstract: An apparatus including a first die mounted on a primary side of an electronic package and a second die mounted on a secondary side of the electronic package between the electronic package and a printed circuit board. The apparatus further comprising a thermal component thermally connected to the second die and mounted on the printed circuit board, the thermal component comprising a set of pins extending from a heat sink through a set of through-holes in the printed circuit board. A method including positioning a set of thermal connectors through a printed circuit board, the thermal connectors extending from a primary side of the printed circuit board to a secondary side of the printed circuit board opposite the primary side. The method further including thermally connecting the thermal connectors to a die positioned between an electronic package and the primary side of the printed circuit board to transfer heat from the die to the secondary side of the printed circuit board.

Abstract: An integrated circuit arrangement including a nonplanar substrate on which an integrated circuit is formed on at least one side, wherein the side of the substrate which has the integrated circuit is arranged on a carrier and the carrier is produced from a chemically resistant material.

Abstract: Support structures for semiconductor devices and methods of manufacturing thereof are disclosed. In some embodiments, the support structures include a plurality of support members that is formed in a substantially annular shape beneath a wire bond region. The central region inside the substantially annular shape of the plurality of support members may be used to route functional conductive lines for making electrical contact to active areas of the semiconductor device. Dummy support structures may optionally be formed between the functional conductive lines. The support structures may be formed in one or more conductive line layers and semiconductive material layers of a semiconductor device. In other embodiments, support members are not formed in an annular shape, and are formed in insulating layers that do not comprise low dielectric constant (k) materials.

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface; a first through wiring penetrating through the semiconductor substrate from the first surface to the second surface; an antenna formed on the first surface and electrically connected to the first through wiring; a semiconductor element formed on the second surface and electrically connected to the first through wiring; a first sealing layer formed on the second surface to cover the semiconductor element; and a first external terminal having one end portion exposed from the first sealing layer and the other end portion electrically connected to the semiconductor element.

Abstract: A semiconductor optical device comprises a lower cladding layer of a first conductive type, an upper cladding layer of a second conductive type, and an active layer. The lower cladding layer has a first region and a second region. The first region extends in a direction of a predetermined axis, and the second region is located adjacent to the first region. The active layer is provided between the first region of the lower cladding layer and the upper cladding layer. The thickness of the active layer is changed in the direction such that TM mode gain and TE mode gain are substantially equal to each other.

Abstract: A high frequency arrangement is provided that includes an integrated high frequency circuit, a first bond pad, which is electrically connected by a first electrical supply line, in particular a bond wire and/or a solder bump, to a housing terminal and/or another circuit, wherein the first bond pad adjoins a dielectric so that the first bond pad forms a first capacitance with the dielectric and an electrically conductive region of the integrated high-frequency circuit, and the first capacitance and the first supply line, which has an inductance, influence a (tuned) first resonant frequency associated with the high-frequency circuit.

Abstract: A semiconductor die including a test structure is provided. The semiconductor die includes a loop-back formed on a surface of the semiconductor die. The loop-back structure includes a first bonding pad on a first surface; and a second bonding pad on the first surface, wherein the first and the second bonding pads are electrically disconnected from integrated circuit devices in the semiconductor die. A conductive feature electrically shorts the first and the second bonding pads. An additional die including an interconnect structure is bonded onto the semiconductor die. The interconnect structure includes a third and a fourth bonding pad bonded to the first and the second bonding pads, respectively. Through-wafer vias in the additional die are further connected to the third and fourth bonding pads.

Abstract: A method and apparatus for partially strapping two polysilicon lines, each having a first end and second end, uses a metal line having a plurality of spaced apart metal segments with each metal segment partially strapping a different portion of a polysilicon line. The metal segments are arranged from the first end to the second end with the signals propagating from the second end to the first end. Where two metal segments are used, the segments have lengths of x = 2 ? L 7 and L?X where L is the length between the first end and the second end. Where three segments are used, the segments have lengths of X=0.25L, Y=0.48L, and Z=0.27L.

Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.

Abstract: A wired circuit board is provided having a high-reliability conductive pattern formed thereon and mounting an electronic component thereon with high accuracy, and a method is provided for manufacturing the wired circuit board and mounting the electronic component thereon. An insulating layer including a mounting portion is formed on a metal supporting layer having a specular gloss of 150 to 500% at an incidence angle of 45°. A conductive pattern is formed on the insulating layer. By a reflection-type optical sensor, a defective shape of the conductive pattern is inspected. Then, an opening is formed by etching the portion of the metal supporting layer which is overlapping the mounting portion such that the mounting portion of the insulating layer exposed by etching has a haze value of 20 to 50%, whereby a TAB tape carrier is obtained.

Abstract: A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80 degrees leading to an aspect ratio higher than 4. The etching process also leads to roughened sidewalls for selective electroless plating on the sidewalls of the polymer structures. These fabricated structures show reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging. Other embodiments are also claimed and described.

Abstract: A semiconductor package has a substrate having a first surface, a second surface, and a through hole opening. A heat spreader has a first surface, a second surface, and a plurality of notches formed on the second surface. A semiconductor die is coupled to the first surface of the heat spreader. The semiconductor die is electrically coupled to the substrate. An encapsulant is used to cover portions of the first surface of the substrate, portions of the first surface of the heat spreader, and the semiconductor die. A first set of solder balls is coupled to the second surface of the substrate. A second set of solder balls is coupled to the second surface of the heat spreader wherein the second set of solder balls is located in the notches.