Abstract: A unit semiconductor chip and stacked semiconductor package and method of manufacturing with center bonding pads and at least one circuit layer to reduce the length of bonding. The unit semiconductor chip includes a first series of bonding wires connected to a plurality of center bonding pads of a semiconductor chip, at least one circuit layer connected to the first series of bonding wires and including a series of circuit layer wiring patterns, and a second series of bonding wires connecting the series of circuit layer wiring patterns and a series of wiring patterns. The stacked semiconductor package further includes a second series of wiring patterns, connected to the first series of wiring patterns, the a second series of wiring patterns and the series of circuit layer wiring patterns providing connections to adjacent lower and upper unit semiconductor packages, respectively.

Abstract: An electronic device to be loaded on an electronic equipment or an electronic component is mounted on a mount substrate, the mount substrate being made thin and flexible and having strong resistance to bending. An electronic device package including: a flexible substrate having a wiring pattern formed thereon; and an electronic device having a terminal formation face on which a connection terminal is provided, wherein the connection terminal is electrically connected directly or via a conductive member to the wiring pattern, and the terminal formation face is substantially aligned in a neutral plane of bending in a thickness direction of the electronic device package.

Abstract: An under bond pad structure is described for integrated circuit dice are that have active circuits located below at least some of the bond pads. The metallization layers interconnection structures within the die are arranged so that electrically conductive vias do not extend between the bond pads and any underlying metallization layer in a region that overlies an active circuit. In some embodiments, no conductive vias are provided between any of the metallization layers in regions that underlie the bond pads and overlie an active circuit. The described arrangements significantly improve the resistance to cracking in the dielectric layers beneath the bond pad (and particularly the topmost intermediate dielectric layer) when wire bonding is used to electrically connect such dice within a package.

Abstract: A method for providing a cavity structure on a semiconductor device is provided. The method of forming the cavity structure, which may be particularly useful in packaging an image sensor, includes forming a spacer layer over a substrate. The spacer layer may be formed from a photo-sensitive material which may be patterned using photolithography techniques to form cavity walls surrounding dies on the wafer. A packaging layer, such as a substantially transparent layer, may be placed directly upon the cavity walls prior to curing. In another embodiment, the cavity walls are cured, an adhesive is applied to a surface of the cavity walls, and the packaging layer placed upon the adhesive. Thereafter, the wafer may be diced and the individual dies may be packaged for use.

Abstract: A package for an integrated circuit includes a chip having a plurality of nodes adapted to receive signals from or to output signals to an external circuit; and a frame having a plurality of contact points each coupled to one node of the chip and to a pad, wherein each pad comprises a nano material.

Abstract: In the semiconductor device of the present invention, there are provided output terminals on two sides perpendicular to one of four sides which is nearest output outer leads of a liquid crystal driver chip mounted to a flexible substrate. The wires extending from the inner leads connected to the output terminals to the output outer leads do not need to travel around a liquid crystal driver chip. The flexible substrate can be scaled down. Yields can be increased.

Abstract: A device and method identify and compensate for tensile stress due to heat-caused expansion and contraction between an integrated heat spreader and thermal interface material. This device and method change the shape of the integrated heat spreader based upon the identification of the location of the highest tensile and/or shear stress so that additional thermal interface material is deposited between the integrated heat spreader and a die. Utilizing this method and device, heat is efficiently transferred from the die to the integrated heat spreader.

Abstract: Packaging and encapsulation methods include use of a tape substrate with a mold gate that includes an aperture and a support element that extends over at least a portion of the aperture. The tape substrate may be part of a strip. A semiconductor device is secured and electrically connected to the tape substrate. The resulting assembly is placed into a cavity of a mold, and encapsulant is introduced into the cavity through the mold gate of the tape substrate. Once the encapsulant has sufficiently hardened, the package assembly may be removed from the mold, and a sprue of residual encapsulant removed therefrom. If the package assembly is carried by a strip that carries other package assemblies, it may be removed from the strip.

Abstract: A composite multi-layer substrate comprising a flat plate-like core member formed of a material having an excellent electric conductivity, an excellent heat conductivity, and a high rigidity, a front resin layer and a rear resin layer covering at least the front and rear surfaces of the core member, and a bottomless hole formed in the core member through the front and rear sides of the core member, wherein an electronic component is installed in the bottomless hole, whereby since the strength of the composite multi-layer substrate can be assured by the rigidity of the core member, conventional prior art glass cloth can be eliminated, deterioration in the electric characteristics caused by ion migration can be avoided and will result in reduced production cost.

Abstract: The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1053) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).

Abstract: The present invention has an object to provide a semiconductor device, an ID tag, in which delay of signal transmission with conductive layers is controlled. In addition, the other object is that a design method of such a semiconductor device is provided. A semiconductor device of the invention comprises a plurality of conductive layers, a plurality of first element groups each of which selects one among the conductive layers and a plurality of second element groups each of which amplifies a signal each transmitted from the conductive layers. Each of the second element groups is disposed between the first element groups. Stated another way, the first element group and the second element group are disposed alternately. The delay of the signal transmission with the plurality of conductive layers is controlled because a load by a parasitic capacitance is reduced due to the above feature.

Abstract: A module substrate includes an insulating substrate, a circuit pattern formed on at least a main surface of the insulating substrate, a protection film formed on the main surface of the insulating substrate including the circuit patter such as to expose a mount region of the circuit pattern, an active element part mounted on the mount region of the circuit pattern, a fluororesin film formed on the protection film at least in a vicinity of the mount region of the active element part, and an underfill filled between the active element part and the mount region of the circuit pattern.

Abstract: A semiconductor module is formed by alternately stacking resin boards on which semiconductor chips are mounted and sheet members having openings larger than the semiconductor chips and bonded to the resin boards. One of the resin boards located at the bottom has a thickness larger than that of each of the other resin boards. First buried conductors formed in each of first resin boards are arranged to form a plurality of lines surrounding a region on which a semiconductor chip is to be mounted. The spacing between the first buried conductors increases in succession toward the outermost line. Second buried conductors formed in each of sheet members are arranged to form a plurality of lines surrounding an opening. The spacing between the second buried conductors increases in succession toward the outermost line.

Abstract: A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.

Abstract: A method for making a titanium carbide layer is described. That method comprises alternately introducing a carbon containing precursor and a titanium containing precursor into a chemical vapor deposition reactor, while a substrate is maintained at a selected temperature. The reactor is operated for a sufficient time, and pulse times are selected for the carbon containing precursor and the titanium containing precursor, to form a titanium carbide layer of a desired thickness and workfunction on the substrate.

Abstract: A carrying structure of electronic components is proposed. The carrying structure includes at least one supporting board with at least one cavity disposed thereon, at least one adhesive layer formed on the supporting board, and at least one electronic component having an active face and a non-active face located in the cavity. The gap between the cavity and the electronic component is filled with a portion of the adhesive layer, and thus the electronic component is fixed in the cavity of the supporting board.

Abstract: In a semiconductor module connecting a semiconductor element and a passive element to a printed board, each of connection portions between the semiconductor element and the printed board and between the passive element and the printed board includes a metal with a melting point of 260° C. or higher and an intermetallic compound with a melting point of 260° C. or higher. Specifically, by connecting them using Pb-free solder with a melting point of 260° C. or lower, the printed board capable of lowering in cost, lightening, and reducing back height can be applied to a module board.

Abstract: A package for an electronic component according to one embodiment of the invention has a chip mounting area mounting a semiconductor chip in a hollow part of a metal plate and a plurality of connection electrodes to be connected to a substrate. The plurality of connection electrodes are formed in opposite sides of the rectangular metal plate and arranged asymmetrically with respect to a perpendicular bisector of the opposite sides.

Abstract: A circuit support for a semiconductor chip with a substrate made of an insulating material has a chip mounting area and a plurality of bonding pads surrounding the chip mounting area. The chip can be applied in a central area of the chip mounting area. A peripheral area surrounding the central area defines the border of the chip mounting area and it is of a far greater length than a length of the lateral edges of the chip to be mounted.

Abstract: A ball grid array housing, a semiconductor device having a ball grid array housing and an electronic circuit are disclosed. In one embodiment, a ball grid array housing includes a substrate with solder ball connections pointing out from a housing and at least one semiconductor chip. For better heat dissipation from the housing, the ball grid includes a metallic cooling foil, or a metallic cooling plate. A method of making a ball grid array is also disclosed.