Patents Examined by Krista Soderholm
  • Patent number: 8314484
    Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: November 20, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Ryoichi Kajiwara, Shigehisa Motowaki, Kazutoshi Ito, Toshiaki Ishii, Katsuo Arai, Takuya Nakajo, Hidemasa Kagii
  • Patent number: 8314483
    Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: November 20, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Patent number: 8309423
    Abstract: A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: November 13, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer P. Pendharkar, Binghua Hu
  • Patent number: 8298963
    Abstract: With a recent shrinking semiconductor process, insulating layers formed between interconnect layers are becoming thin. To avoid parasitic capacitance between them, materials of a low dielectric constant have been used for an insulating layer in a multilevel interconnect. Low-k materials, however, have low strength compared with the conventional insulating layers. Porous low-k materials are structurally fragile. The invention therefore provides a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer. According to the method, in a two-step cutting system dicing in which after formation of a groove in a semiconductor water with a tapered blade, the groove is divided with a straight blade thinner than the groove width, the multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiko Akiba, Minoru Kimura, Masao Odagiri
  • Patent number: 8299600
    Abstract: A semiconductor device is provided with improved reliability. A semiconductor chip is mounted over a chip mounting portion of a lead frame via solder. A metal plate is arranged over a source pad of the semiconductor chip and a lead portion of a lead frame via solder. A solder reflow process is performed thereby to bond the semiconductor chip over the chip mounting portion with a solder, and to bond the metal plate to the source pad and the lead portion with the other solders. The lead frame is formed of a copper alloy, and thus has its softening temperature higher than the temperature of the solder reflow process. The metal plate is formed of oxygen-free copper, and has its softening temperature lower than the temperature of the solder reflow process, whereby the metal plate is softened in the solder reflow process. Thereafter, a gate pad electrode of the semiconductor chip is coupled to a lead portion via the wire, a sealing resin portion is formed, and then the lead frame is cut.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yukihiro Sato, Katsuhiko Funatsu, Hiroyuki Nakamura
  • Patent number: 8288814
    Abstract: A semiconductor die includes a first set of metal lines and a second set of metal lines. The first set of metal lines and the second set of metal lines are placed in alternate planes and are orthogonal to each other. A via is used to connect a first metal line from the first set of metal lines with a second metal line from the second set of metal lines. The via location is offset such that a side of the first metal line is aligned with a side of the second metal line. Consequently, a metal line adjacent to the first metal line does not need to detour around the via.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: October 16, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Pankaj K Jha, Rajesh Bansal, Chetan Verma
  • Patent number: 8264066
    Abstract: An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: September 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Lo, Hung-Jung Tu, Hai-Ching Chen, Tien-I Bao, Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 8251644
    Abstract: An engine blower includes a centrifugal blower, an engine, and a frame for supporting the centrifugal blower. The centrifugal blower is supported by a back support of the frame via a flexible vibration-proofing section while being connected to the back support via a belt-shaped stopper. An engaging hole is provided on at least one of the centrifugal blower and the back support, and a thick engaging section is provided on at least one end of the stopper for being engaged with the engaging hole. When the stopper is inserted into the engaging hole and the one end of the stopper is pulled, the engaging section is engaged with the engaging hole. By further pulling the one end of the stopper, the engaging section is tightly buried into the engaging hole. Thus, the stopper can be reliably attached to the centrifugal blower or the back support.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: August 28, 2012
    Assignee: Husqvarna Zenoah Co., Ltd.
    Inventors: Shinichi Wada, Ryou Ono, Ryouji Zama
  • Patent number: 8235659
    Abstract: A lanced and/or slit seamed housing and method of manufacture having a peripheral rolled and lanced or punched seam between a wrapper and the housing panels. The method of manufacture utilizes similar or dissimilar sheet materials in a variety of material thicknesses and with or without coatings applied prior to formation whereby a housing is formed quickly and safely. The rolling and lancing method manufactures a blower housing with an assured and positive sealed seam between the panels and wrapper of the housing. The lances or slits maintain the integrity of the seam and prevent slippage between the wrapper and panels.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: August 7, 2012
    Assignee: Custom Rollform Products, Inc.
    Inventor: Larry Slavik
  • Patent number: 8237278
    Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Yunsheng Song, Tso-Hui Ting, Ping-Chuan Wang
  • Patent number: 8232646
    Abstract: An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Chao-Kun Hu, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
  • Patent number: 8231337
    Abstract: The invention relates to a pump for pumping contaminated liquid including solid matter, comprising a pump housing provided with a rotatable impeller suspended in a drive shaft and having at least one vane, and an impeller seat, at least one part of the impeller and the impeller seat being movable in the axial direction in relation to each other. Furthermore, the impeller seat presents at least one groove in the top surface thereof.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: July 31, 2012
    Assignee: Xylem IP Holdings LLC
    Inventor: Patrik Andersson
  • Patent number: 8231341
    Abstract: A hybrid gas compressor has at least one rotor and shroud which define a compressor gas path extending from an inlet to an outlet. The compressor includes at least two compression stages and one diffusion stage between the inlet and outlet, the compression stages including respective circumferential arrays of blades extending from the rotor and the diffusion stage including a circumferential array of vanes between the compression stages. Blade aerodynamic loadings may be controlled, particularly in the last stage, to provide desired compression characteristics across the compressor. A bleed outlet is optionally located between the inlet and outlet for bleeding from the gas path.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: July 31, 2012
    Assignee: Pratt & Whitney Canada Corp.
    Inventors: Stephen A. Anderson, Ronald Trumper, Gary Weir
  • Patent number: 8222745
    Abstract: An electronic device includes a heat dissipating component located over a substrate. An isolation trench is formed in the substrate adjacent the component. A contact region of the substrate is bounded by the trench. An electrically isolated contact is located over and in contact with the contact region. The electrically isolated contact and the contact region provide a thermally conductive path to the substrate.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: July 17, 2012
    Assignee: LSI Corporation
    Inventors: Sangjune Park, Carl Iwashita
  • Patent number: 8217501
    Abstract: A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts; attaching an integrated circuit to the top surface; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that are over and larger than the electrical contacts.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: July 10, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Hyeog Chan Kwon, Hyun Joung Kim, Jae Chang Kim, Taeg Ki Lim, Jong Wook Ju
  • Patent number: 8210806
    Abstract: A ventilator (100) includes a frame (10), a volute (20) mounted in the frame (10), a motor bracket (60) mounted in the opening of the volute (20) and a motor (30) fitted in the motor bracket (60). The frame (10) is made of metal material. The character of the ventilator is in that the motor bracket (60) is made of metal material. Since the metal motor bracket has favorable performances of heat radiation and rigidity, the ventilator (100) has better security and stability.
    Type: Grant
    Filed: February 25, 2007
    Date of Patent: July 3, 2012
    Assignees: Panasonic Corporation, Panasonic Ecology Systems, Guangdong Co., Ltd.
    Inventors: Jingtao Yang, Guangzhu Xuan, Zewei Rao
  • Patent number: 8212363
    Abstract: A multilayer printed wiring board including insulating layers, conductor layers stacked alternately over the insulating layers, respectively, and viaholes formed in the insulation layers and electrically connecting the conductor layers through the insulation layers. The viaholes include a first group of viaholes and a second group of viaholes. The viaholes in the first group are tapered toward the viaholes in the second group, and the viaholes in the second group are tapered toward the viaholes in the first group. The viaholes in the first group and the the viaholes in the second group are formed in the insulating layers, respectively, and the viaholes are formed by plating openings formed after lamination of respective ones of the insulating layers, and each of the insulating layers is about 100 ?m or less in thickness.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: July 3, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Michimasa Takahashi, Yukinobu Mikado, Takenobu Nakamura, Masakazu Aoyama
  • Patent number: 8212367
    Abstract: An integrated circuit (IC) die includes two bonding pads, that share a common logical function, such as signal input or signal output, separated by the width of the die, and preferably on opposite sides of the die. System-in-package devices are produced by steps including directly electrically connecting one or the other bonding pad to bonding pads of other, functionally different IC dies, with the bonding pads of the other IC dies, to which are connected bonding pads of common logical function of the IC dies of the present invention, being functionally identical but geometrically different. Multchip package devices are produced by stacking the IC dies of the present invention with other IC dies and directly electrically connecting one or the other bonding pad to different bonding pads of the other IC dies.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: July 3, 2012
    Assignee: SanDisk IL Ltd.
    Inventor: Amir Ronen
  • Patent number: 8206085
    Abstract: In one embodiment, a system includes a turbine engine that includes a rotor including multiple blades. The turbine engine also includes a shroud disposed about the blades. The shroud includes multiple segments engaged with one another via mating teeth. The mating teeth are oriented in an axial direction along a longitudinal axis of the turbine engine.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: June 26, 2012
    Assignee: General Electric Company
    Inventor: Luke J. Ammann
  • Patent number: 8197192
    Abstract: The invention relates to a pump for pumping contaminated liquid including solid matter, comprising an impeller (1), which is rotatable in a pump chamber of said pump, the impeller (1) being movable in the axial direction in relation to a seal housing cover (3) between a first position adjacent to an impeller seat (2) and a second position spaced apart from said impeller seat (2), said pump also comprising a cavity (17) defined by the seal housing cover (3) and the impeller (1), and at least one opening gap (20) connecting said cavity and said pump chamber. Furthermore, said opening gap (20) has a first flow area when the impeller (1) is in the first position, and a second flow area bigger than said first flow area when the impeller (1) is' spaced apart from said first position.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: June 12, 2012
    Assignee: Xylem IP Holdings LLC
    Inventor: Patrik Andersson