Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. The first semiconductor structure or the second semiconductor structure further includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first peripheral circuit and the second peripheral circuit are stacked over one another.

Abstract: A semiconductor device and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a substrate, a semiconductor structure, a gate dielectric layer, and a first gate. The semiconductor structure is disposed above the substrate and includes two thick portions and a thin portion located between the two thick portions. A thickness of the two thick portions is larger than a thickness of the thin portion. The gate dielectric layer is disposed on the semiconductor structure. The first gate is disposed on the gate dielectric layer. A width of the first gate is smaller or equal to a width of the thin portion, and the first gate is overlapped with the thin portion in a normal direction of a top surface of the substrate. A doping concentration of the two portions is larger than a doping concentration of the thin portion.

Abstract: A manufacturing method of a package system includes: providing a base plate with a first thermal interface material (TIM) layer; placing a semiconductor package on the first TIM layer over the base plate, wherein the semiconductor package comprises a plurality of packaging units arranged in an array and a plurality of electrical connectors surrounding the array of the plurality of packaging units; stacking a gasket and a top plate on the array of the plurality of packaging units, wherein the gasket is interposed between the top plate and the array of the plurality of packaging units; and securing the top plate, the gasket, the plurality of packaging units, and the base plate together through a plurality of fasteners, wherein each of the plurality of fasteners is arranged at a gap between two of the adjacent packaging units.

Abstract: Data received from an in-situ monitoring system includes, for each scan of a sensor, a plurality of measured signal values for a plurality of different locations on a layer. A thickness of a polishing pad is determined based on the data from the in-situ monitoring system. For each scan, a portion of the measured signal values are adjusted based on the thickness of the polishing pad. For each scan of the plurality of scans and each location of the plurality of different locations, a value is generated representing a thickness of the layer at the location. This includes processing the adjusted signal values using one or more processors configured by machine learning. A polishing endpoint is detected or a polishing parameter is modified based on the values representing the thicknesses at the plurality of different locations.

Abstract: A display module includes a display panel, a flexible printed circuit, a composite adhesive layer, and at least one conductive structure. The display panel includes a base substrate. The flexible printed circuit includes at least one first conductive region, and is electrically connected to the display panel. The composite adhesive layer is located at one side of the base substrate away from a light emission surface of the display panel. The composite adhesive layer includes at least one first through hole penetrating through the composite adhesive layer, and the conductive structure is at least partially located within the first through hole. Along a direction perpendicular to a plane where the base substrate is located, length of the composite adhesive layer is H1, and length of the conductive structure is H2, where H1?H2. The conductive structure is electrically connected to the first conductive region.

Abstract: A transistor device includes a semiconductor substrate and a gate structure formed over the substrate. Forming the gate structure may include steps of forming a multi-layer dielectric stack over the substrate, performing an anisotropic dry etch of the multi-layer dielectric stack to form a gate channel opening, forming a conformal dielectric layer over the substrate, performing an anisotropic dry etch of the conformal dielectric layer to form dielectric sidewalls in the gate channel opening, etching portions of dielectric layers in a gate channel region, and forming gate metal in the gate channel region. Dielectric spacers may be similarly formed in a field plate channel opening prior to formation of a field plate of the transistor. By forming dielectric spacers in the gate channel opening, the length of the gate structure can be advantageously decreased.

Abstract: A stack type semiconductor device including a first wafer and a second wafer. The first wafer including at least one first chip. The second wafer including at least one second chip electrically connected with the first chip. Each of the first and second chips including a test circuit block, at least one test bonding pad and a hybrid boning member. The test circuit block performing a test operation based on a test signal. The test bonding pad arranged on a bonding surface of each of the first and second chips to transmit the test signal and signals for driving the test circuit block between the first and second chips. The hybrid bonding member electrically connected between the test bonding pads.

Abstract: A package assembly includes a package substrate, a solder resist layer on the package substrate and including an elongated solder resist opening, and an interposer module on the package substrate and including a corner located on the elongated solder resist opening.

Abstract: A display device includes a first substrate, a plurality of light emitting elements that is provided on the first substrate, a second substrate that is provided so as to face a plurality of the light emitting elements, a wall portion that is provided on the first substrate, surrounds an effective pixel area, and supports the second substrate, and a filling resin layer with which a space surrounded by the first substrate, the second substrate, and the wall portion is filled.

Abstract: A semiconductor device is provided. The semiconductor device includes a logic structure overlying a semiconductor substrate of the semiconductor device. The logic structure includes a plurality of logic cells. The semiconductor device includes one or more interconnection layers, overlying the logic structure, in a Back End of Line (BEOL) structure of the semiconductor device. The semiconductor device includes a non-volatile memory array, including a plurality of memory cells, overlying the logic structure and the one or more interconnection layers, wherein the non-volatile memory array at least one of overlies or is within the BEOL structure.

Abstract: A chip package and a method of fabricating the same are disclosed. The chip package includes a substrate with a first region, a second region surrounding the first region, and a third region surrounding the second region, a device layer disposed on the substrate, a via layer disposed on the device layer, an interconnect structure disposed on the via layer, and a stress buffer layer with tapered side profiles disposed on the interconnect structure. First and second portions of the via layer above the first and second regions include first and second set of vias. First, second, and third portions of the interconnect structure above the first, second, and third regions include conductive lines connected to the devices, a first set of dummy metal lines connected to the second set of vias, and a second set of dummy metal lines.

Abstract: A semiconductor package includes a frame, a semiconductor chip, a through via, a connection pad, a lower redistribution layer on the bottom surfaces of the frame and the semiconductor chip, a connection terminal on the lower redistribution layer, an encapsulant covering the top surfaces of the frame and the semiconductor chip, and an upper redistribution layer on the encapsulant. The lower redistribution layer includes a lower insulating layer, a lower redistribution pattern, and an under-bump metal (UBM). The upper redistribution layer includes an upper insulating layer, an upper redistribution pattern, an upper via, and an upper connection pad. The lower insulating layer includes an inner insulating pattern surrounding the side surface of the UBM and an outer insulating pattern surrounding the side surface of the inner insulating pattern. The cyclization rate of the inner insulating pattern is higher than the cyclization rate of the outer insulating pattern.

Abstract: A chip packaging structure and a chip packaging method are provided. The chip packaging structure includes a first substrate, an image sensing chip, a supporting member, a second substrate, and an encapsulant. The image sensing chip is disposed on an upper surface of the first substrate, and the image sensing chip has an image sensing region. The supporting member is disposed on an upper surface of the image sensing chip and surrounds the image sensing region. The supporting member is formed by stacking microstructures with each other, so that the supporting member has pores. The second substrate is disposed on an upper surface of the supporting member, and the second substrate, the supporting member, and the image sensing chip define an air cavity. The encapsulant is attached to the upper surface of the first substrate and a side surface of the second substrate and filled into the pores.

Abstract: A method for forming semiconductor structure includes: providing a semiconductor substrate, which at least includes discrete conducting layers in the semiconductor substrate; forming discretely arranged supporting structures on the semiconductor substrate, lower portions of the supporting structures including a bottom conducting layers, and capacitor openings being included between the supporting structures, and the bottom conducting layers being electrically connected with the conducting layers; forming lower electrodes on sidewalls of the supporting structures, the lower electrodes being electrically connected with the bottom conducting layers; forming a capacitor dielectric layer covering tops of the supporting structures, sidewalls of the lower electrodes, and bottoms of the capacitor openings; and forming an upper electrode covering the capacitor dielectric layer), to form a capacitor structure. A semiconductor structure is also provided.

Abstract: Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example.

Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a plurality of photodetectors disposed within a substrate, and the plurality of photodetectors includes a first active photodetector and a black level correction (BLC) photodetector. A metal grid structure surrounds the first active photodetector along a periphery of the first active photodetector on a first side of the substrate. A recessed blocking structure covers the BLC photodetector on the first side of the substrate. The recessed blocking structure includes both a first blocking layer inset into the first side of the substrate and a second blocking layer directly over the first blocking layer.

Abstract: A display substrate is provided. The display substrate includes: a substrate; a light emitting layer arranged on a side of the substrate; an encapsulation layer arranged on a side of the light emitting layer away from the substrate; and at least two dams arranged around a display area in a non-display area. The encapsulation layer includes an organic material layer, and the dams include a first dam arranged around the display area and a second dam arranged around the first dam, where the first dam includes a first sub-dam arranged discontinuously, a second sub-dam arranged continuously, and at least one third sub-dam connecting the first sub-dam and the second sub-dam; the first sub-dam, the second sub-dam, and the third sub-dam are arranged around to form at least one semi-closed region structure; and at least a part of the organic material layer is located in the semi-closed region structure.

Abstract: A semiconductor structure includes an assembly including an interposer, at least one semiconductor die attached to the interposer including interposer bonding pads, and a die-side underfill material portion located between the interposer and the at least one semiconductor die, a packaging substrate including substrate bonding pads, an array of solder material portions bonded to the interposer bonding pads and the substrate bonding pads, a central underfill material portion laterally surrounding a first subset of the solder material portions, and at least one peripheral underfill material portion contacting corner regions of the interposer and a respective surface segment of the central underfill material portion and having a different material composition than the central underfill material portion.

Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.