Abstract: There is provided a technique, including: (a) forming NH termination on a surface of a substrate by supplying a first reactant containing N and H to the substrate; (b) forming a first SiN layer having SiCl termination formed on its surface by supplying SiCl4 as a precursor to the substrate to react the NH termination formed on the surface of the substrate with the SiCl4; (c) forming a second SiN layer having NH termination formed on its surface by supplying a second reactant containing N and H to the substrate to react the SiCl termination formed on the surface of the first SiN layer with the second reactant; and (d) forming a SiN film on the substrate by performing a cycle a predetermined number of times under a condition where the SiCl4 is not gas-phase decomposed after performing (a), the cycle including non-simultaneously performing (b) and (c).

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

Abstract: A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.

Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; one or multiple vias penetrating the active layer and the second semiconductor layer to expose the first semiconductor layer; a first contact layer covering the one or multiple vias; a third insulating layer including a first group of one or multiple third insulating openings on the second semiconductor layer to expose the first contact layer; a first pad on the semiconductor stack and covering the first group of one or multiple third insulating openings; and a second pad on the semiconductor stack and separated from the first pad with a distance, wherein the second pad is formed at a position other than positions of the one or multiple vias in a top view of the light-emitting device.

Abstract: A deposition mask group includes a first deposition mask having two or more first through holes arranged along two different directions, a second deposition mask having two or more second through holes arranged along two different directions and a third deposition mask having two or more third through holes. The first through hole and the second through hole or the third through hole partly overlap when the first deposition mask, the second deposition mask and the third deposition mask are overlapped.

Abstract: A system and method for growing a gallium nitride (GaN) structure that includes providing a template; and growing at least a first GaN layer on the template using a first sputtering process, wherein the first sputtering process includes: controlling a temperature of a sputtering target, and modulating between a gallium-rich condition and a gallium-lean condition, wherein the gallium-rich condition includes a gallium-to-nitrogen ratio having a first value that is greater than 1, and wherein the gallium-lean condition includes the gallium-to-nitrogen ratio having a second value that is less than the first value. Some embodiments include a load lock configured to load a substrate wafer into the system and remove the GaN structure from the system; and a plurality of deposition chambers, wherein the plurality of deposition chambers includes a GaN-deposition chamber configured to grow at least the first GaN layer on a template that includes the substrate wafer.

Abstract: An organic light emitting display including a substrate, a first electrode and a second electrode on the substrate and facing each other, at least two organic light emitting layers between the first electrode and the second electrode, and at least two color filters on the second electrode, the organic light emitting layers emitting a first color light, and the color filters emitting a second color light and a third color light.

Abstract: A display device including a plurality of pixels arranged in a matrix, a substrate, a first anode disposed on the substrate, and a plurality of opaque conductive layers disposed between the substrate and the first anode, in which the pixels include an opening pixel including a first anode arrangement region, a pinhole region located around the first anode arrangement region and surrounded by the first anode, and a first anode non-arrangement region including an exposed region located outside the first anode, and in a plan view, the opaque conductive layers completely cover the exposed region and at least partially expose the pinhole region.

Abstract: A display apparatus includes a substrate including a display area, a non-display area adjacent to the display area, and a pad area arranged in the non-display area; a display portion arranged in the display area and including pixels; a pad portion arranged in the pad area and including pads; and an insulating layer overlapping an edge of each of the pads and exposing a central portion of each of the pads, wherein the insulating layer includes at least one opening arranged between adjacent ones of the pads.

Abstract: In accordance with disclosed embodiments, there is a method of integrating and accessing passive components in three-dimensional fan-out wafer-level packages. One example is a microelectronic die package that includes a die, a package substrate attached to the die on one side of the die and configured to be connected to a system board, a plurality of passive devices over a second side of the die, and a plurality of passive device contacts over a respective passive die, the contacts being configured to be coupled to a second die mounted over the passive devices and over the second side of the die.

Abstract: A display device is provided with a display area and a frame area on a flexible substrate. The display area includes a transistor and a light-emitting element, and the frame area surrounds the display area. The display device includes: an upper inorganic insulating film, a first upper metal layer, a first resin layer, a protective layer, a second upper metal layer, a second resin layer, and a third resin layer provided in a stated order above a semiconductor layer of a transistor. In a display area, the protective layer covering a whole upper face of the first resin layer comes into contact with an upper wire included in the second upper metal layer.

Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.

Abstract: A semiconductor package includes a supporting wiring structure including a first redistribution dielectric layer and a first redistribution conductive structure; a frame on the supporting wiring structure, having a mounting space and a through hole, and including a conductive material; a semiconductor chip in the mounting space and electrically connected to the first redistribution conductive structure; a cover wiring structure on the frame and the semiconductor chip and including a second redistribution dielectric layer and a second redistribution conductive structure; an antenna structure on the cover wiring structure; a connection structure extending in the through hole and electrically connecting the first redistribution conductive structure to the second redistribution conductive structure; and a dielectric filling member between the connection structure in the through hole and the frame and surrounding the semiconductor chip, the frame, and the connection structure.

Abstract: Provided is a display device including a base layer; a light emitting element layer disposed on the base layer; and a thin-film encapsulation layer disposed on and encapsulating the light emitting element layer, where the thin-film encapsulation layer includes an inorganic layer having at least one inorganic sub-layer pair, where the at least one inorganic sub-layer pair includes a first inorganic sub-layer having a first refractive index and a second inorganic sub-layer disposed on the first inorganic sub-layer and having a second refractive index different from the first refractive index.

Abstract: A display device includes: a display panel; and an input sensing unit disposed on the display panel and including an active area and a peripheral area adjacent to the active area; wherein the input sensing unit includes: a first conductive layer disposed on at least the peripheral area; a first insulation layer disposed on the first conductive layer exposing at least a portion of the first conductive layer; a second conductive layer disposed on the first insulation layer and including sensing patterns; and a second insulation layer including an organic material disposed on the second conductive layer.

Abstract: A display device includes: a display panel in which a first panel region, a bending region, and a second panel region are arranged along a first direction; a support layer below the first panel region of the display panel, wherein the bending region of the display panel is bent toward a lower portion of the support layer; a portion of the support layer is between the first panel region and the second panel region; a first alignment mark in the first panel region; and a first alignment opening overlapping the first alignment mark in the support layer, wherein in a thickness direction of the display panel, the first alignment opening is spaced apart from the second panel region, the first alignment opening is spaced apart from an edge of the support layer, and the first alignment opening is completely surrounded by the support layer.

Abstract: Some embodiments provide a method for executing a neural network that includes multiple nodes. The method receives an input for a particular execution of the neural network. The method receives state data that includes data generated from at least two previous executions of the neural network. The method executes the neural network to generate a set of output data for the received input. A set of the nodes performs computations using (i) data output from other nodes of the particular execution of the neural network and (ii) the received state data generated from at least two previous executions of the neural network.

Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a substrate structure, a redistribution structure, an adhesive layer and at least one conductive pillar. The redistribution structure includes at least one dielectric layer. The at least one dielectric layer defines at least one through hole extending through the dielectric layer. The adhesive layer is disposed between the redistribution structure and the substrate structure and bonds the redistribution structure and the substrate structure together. The at least one conductive pillar extends through the redistribution structure and the adhesive layer and is electrically connected to the substrate structure. A portion of the at least one conductive pillar is disposed in the through hole of the at least one dielectric layer.

Abstract: The present disclosure relates to an artificial intelligence chip for processing computations for machine learning models that provides a compute node and a method of processing a computational model using a plurality of compute nodes in parallel. In some embodiments, the compute node, comprises: a communication interface configured to communicate with one or more other compute nodes; a memory configured to store shared data that is shared with the one or more other compute nodes; and a processor configured to: determine an expected computational load for processing a computational model for input data; obtain a contributable computational load of the compute node and the one or more other compute nodes; and select a master node to distribute the determined expected computational load based on the obtained contributable computational load. Consequently, learning and inference can be performed efficiently on-device.

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.