Patents Examined by Kyoung Lee
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Patent number: 12045708Abstract: An analog element for use as a neuron in a recurrent neural network is described, the analog element having memory of a prior layer state and being a continuous time circuit rather than having a discrete clocking interval. The element is characterized and described by the Laplace s-domain operator, as distinct from a digital solution that uses the z-domain operator appropriate for quantized time descriptions. Rather than using an all-pass filter, the analog equivalent of a unit delay in the z-domain, a finite gain integrator, which is a simpler circuit, may be used to provide the delay in the analog s-domain. The resulting circuit may be easily implemented at the transistor level.Type: GrantFiled: August 8, 2022Date of Patent: July 23, 2024Assignee: SiliconIntervention Inc.Inventor: A. Martin Mallinson
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Patent number: 12041838Abstract: A touch display device is provided. At least one touch electrode includes a first part corresponding to each of at least one additional function area and a second part corresponding to a normal display area. Length and width of at least one trace of a connecting part between each adjacent two of touch sensing parts in the first part are increased to reduce capacitance difference between the first part and the second part. Areas without any pixel unit in each of the at least one additional function area form light transmissive areas, respectively. Thus, a transmission percentage is increased. Touch and display functions of each of at least one additional function area are ensured to be normal, and the transmission percentage is increased at the same time.Type: GrantFiled: July 30, 2023Date of Patent: July 16, 2024Inventor: Yuan Zheng
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Patent number: 12041820Abstract: In a method for manufacturing an active matrix substrate, forming of an underlayer inorganic insulating film includes applying a resist onto the underlayer inorganic insulating film, performing an ashing process of forming a surface having irregularities on a surface of the resist by a first ashing process, and, after the ashing process has been performed, roughening a surface of the underlayer inorganic insulating film by performing a second ashing process and an etching process on the underlayer inorganic insulating film. When forming a semiconductor film, a surface of at least a part of the semiconductor film is roughened following a rough surface of the underlayer inorganic insulating film.Type: GrantFiled: September 6, 2018Date of Patent: July 16, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Takao Saitoh, Masahiko Miwa, Yohsuke Kanzaki, Yi Sun, Masaki Yamanaka, Seiji Kaneko
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Patent number: 12040247Abstract: A package system and a manufacturing method thereof are provided. The package system includes a semiconductor package and a thermal-dissipating structure. The semiconductor package includes a first surface and a second surface opposing to each other, and a planarity of the second surface is greater than that of the first surface. The thermal-dissipating structure includes a first plate secured to the semiconductor package, a gasket interposed between the first plate and the semiconductor package, a second plate secured to the semiconductor package opposite to the first plate, and a first thermal interface material layer interposed between the second plate and the second surface of the semiconductor package. The gasket includes a plurality of hollow regions corresponding to portions of the first surface of the semiconductor package.Type: GrantFiled: May 13, 2021Date of Patent: July 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Hsuan Lee, Ching-Hua Hsieh, Chien-Ling Hwang
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Patent number: 12035589Abstract: The present disclosure discloses a display substrate and a display device. The display substrate comprises: a display area, a binding area, and a fan-out area located between the display area and the binding area, the fan-out area comprises a touch control lead wire, a data lead wire, and at least one shielded wire located between the touch control lead wire and the data lead wire, and the at least one shielded wire is grounded or connected to a fixed potential.Type: GrantFiled: October 21, 2021Date of Patent: July 9, 2024Assignee: BOE Technology Group Co., Ltd.Inventors: Can Zheng, Libin Liu, Shiming Shi, Zewen Bo
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Patent number: 12034099Abstract: A pixel structure, including a first semiconductor layer, a first active layer, a second semiconductor layer, a second active layer, a third semiconductor layer, and an electrode layer that are sequentially stacked, is provided. A first portion of the electrode layer is electrically connected to a first portion of the first semiconductor layer through a first opening of a first portion of the third semiconductor layer, a first opening of a first portion of the second active layer, a first opening of a first portion of the second semiconductor layer, and a first opening of a first portion of the first active layer. A second portion of the electrode layer is electrically connected to a second portion of the second semiconductor layer through a second opening of a second portion of the third semiconductor layer and a second opening of a second portion of the second active layer.Type: GrantFiled: November 3, 2021Date of Patent: July 9, 2024Assignee: Au Optronics CorporationInventors: Yi-Hong Chen, Chia-An Lee, Kuan-Heng Lin
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Patent number: 12029100Abstract: A method for manufacturing a display device includes a mounting process in which a frame terminal of a flexible display panel and a counter terminal of a flexible printed circuit substrate are electrically connected by thermocompression bonding. In the mounting process, the thermocompression bonding is performed in a state in which the flexible display panel is folded so that the flexible display panel includes an abutting portion abutting on a mounting stage and a folding portion where the flexible display panel is to be folded over the abutting portion in plan view.Type: GrantFiled: April 19, 2019Date of Patent: July 2, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Katsuhiro Yamaguchi, Tadashi Nishioka, Keiji Aota
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Patent number: 12027478Abstract: A method of forming a semiconductor structure includes forming a first redistribution structure including a first conductive pattern. The method further includes placing a die over the first redistribution structure. The method further includes disposing a molding material over the first redistribution structure to surround the die. The method further includes removing a portion of the molding material to form an opening. The method further includes disposing a dielectric material into the opening to form a dielectric member. The method further includes forming a second redistribution structure over the molding material and the dielectric member, wherein the second redistribution structure includes an antenna structure over the dielectric member and electrically connected to the die.Type: GrantFiled: June 22, 2022Date of Patent: July 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng-Wei Kuo, Wen-Shiang Liao
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Patent number: 12027645Abstract: An optoelectronic semiconductor chip may have or include an x-doped region, a y-doped region, an active region arranged between the x-doped region and the y-doped region, and an x-contact region. The x-contact region may be arranged to the side of the x-doped region facing away from the active region. The x-contact region may include at least one first region and at least one second region. The x-contact region may be designed such that, during operation of the optoelectronic semiconductor chip, more charge carriers are injected into the x-doped region via the second region than via the first region.Type: GrantFiled: October 2, 2019Date of Patent: July 2, 2024Assignee: OSRAM OPTO SEMICONDUCTORS GMBHInventors: Ivar Tangring, Korbinian Perzlmaier
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Patent number: 12022704Abstract: A display apparatus can include a substrate including a display area and a non-display area adjacent to the display area, a first thin film transistor in the display area, and a second thin film transistor in the display area. The first thin film transistor can include a first semiconductor pattern on the substrate, a first gate electrode overlapping the first semiconductor pattern, and a first source electrode and a first drain electrode both connected to the first semiconductor pattern. The second thin film transistor can include a second semiconductor pattern, a second gate electrode overlapping the second semiconductor pattern, a second source electrode connected to the second semiconductor pattern, and a second drain electrode connected to the second semiconductor pattern. The display apparatus can further include a conductive pattern between the display area and the second semiconductor pattern.Type: GrantFiled: February 3, 2023Date of Patent: June 25, 2024Assignee: LG DISPLAY CO., LTD.Inventors: Kyeong-Ju Moon, So-Young Noh, Ki-Tae Kim, Hyuk Ji
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Patent number: 12015018Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a first molding layer on the first redistribution substrate and covering a top surface and lateral surfaces of the first semiconductor chip, a second redistribution substrate on the first molding layer, and an adhesive film between the second redistribution substrate and the first molding layer. The adhesive film is spaced apart from the first semiconductor chip and covers a top surface of the first molding layer. A lateral surface of the adhesive film is coplanar with a lateral surface of the second redistribution substrate.Type: GrantFiled: December 1, 2022Date of Patent: June 18, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyeonjeong Hwang, Kyoung Lim Suk, Seokhyun Lee, Jaegwon Jang
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Patent number: 12009282Abstract: A memory device includes: a wiring substrate including a multilevel wiring layer and first and second surfaces at opposite sides; a control element embedded in the wiring substrate and having first and second element surfaces at opposite sides, with multiple electrode pads connected to the multilevel wiring layer at the first element surface; a first heat dissipation member at a region of the first surface overlapping the control element; a heat dissipation structure facing the second element surface and exposed at the second surface; and at least one memory element connected with the multilevel wiring layer at a first surface region not overlapping the control element. The multilevel wiring layer includes a signal pattern electrically connecting the control element with the memory element or the external connection terminal, and a heat dissipation conductor pattern forming a heat dissipation path between the control element and the first heat dissipation member.Type: GrantFiled: March 11, 2021Date of Patent: June 11, 2024Assignee: MEIKO ELECTRONICS CO., LTD.Inventor: Shuzo Akejima
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Patent number: 12009201Abstract: There is provided a technique, including: (a) forming NH termination on a surface of a substrate by supplying a first reactant containing N and H to the substrate; (b) forming a first SiN layer having SiCl termination formed on its surface by supplying SiCl4 as a precursor to the substrate to react the NH termination formed on the surface of the substrate with the SiCl4; (c) forming a second SiN layer having NH termination formed on its surface by supplying a second reactant containing N and H to the substrate to react the SiCl termination formed on the surface of the first SiN layer with the second reactant; and (d) forming a SiN film on the substrate by performing a cycle a predetermined number of times under a condition where the SiCl4 is not gas-phase decomposed after performing (a), the cycle including non-simultaneously performing (b) and (c).Type: GrantFiled: March 24, 2023Date of Patent: June 11, 2024Assignee: Kokusai Electric CorporationInventors: Katsuyoshi Harada, Tatsuru Matsuoka, Yoshitomo Hashimoto
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Patent number: 12009792Abstract: Example embodiments relate to power amplifiers with decreased RF return current losses. One embodiment includes a RF power amplifier package that includes a semiconductor die, an input lead, first bondwire connections, second bondwire connections, and a plurality of shields. The semiconductor die includes an RF power transistor that includes output bond pads, input bond pads, a plurality of input fingers, and a plurality of output fingers. Further, each shield of the plurality of shields is arranged in between a respective input finger of the plurality of input fingers and a respective output finger of the plurality of output fingers and extending along with said respective input finger and output finger. In addition, each shield of the plurality of shields is connected to a ground terminal of the RF power transistor. The input fingers, output fingers, and shields are formed using a metal layer stack of multiple metal layers.Type: GrantFiled: September 3, 2019Date of Patent: June 11, 2024Assignee: Ampleon Netherlands B.V.Inventors: Vittorio Cuoco, Jos Van Der Zanden, Yi Zhu, Iouri Volokhine
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Patent number: 11996345Abstract: A package structure includes a first semiconductor die, a first insulating encapsulation, a thermal coupling structure, and a heat dissipating component thermally coupled to the first semiconductor die through the thermal coupling structure. The first semiconductor die includes an active side, a rear side, and a sidewall connected to the active side and the rear side. The first insulating encapsulation extends along the sidewall of the first semiconductor die and includes a first side substantially leveled with the active side, a second side opposite to the first side, and topographic features at the second side. The thermal coupling structure includes a metallic layer overlying and the rear side of the first semiconductor die and the topographic features of the first insulating encapsulation. A manufacturing method of a package structure is also provided.Type: GrantFiled: August 27, 2021Date of Patent: May 28, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11997909Abstract: The present disclosure relates to a display device including an optical device, more specifically, it relates to a display device in which the optical device is positioned under the display panel so that the optical device is not exposed in the front direction. Even if the optical device is located under the display panel, the display device can normally perform the function of the optical device related to the front direction of the display panel and have a structure for this.Type: GrantFiled: January 3, 2023Date of Patent: May 28, 2024Assignee: LG Display Co., Ltd.Inventors: JongHee Hwang, KiDuk Kim
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Patent number: 11996331Abstract: A method for separating a solid body includes: providing a first solid body having opposite first and second surfaces and a crystal lattice, and that is at least partially transparent to a laser beam emitted by a laser; modifying a portion of the crystal lattice by the laser beam, the laser beam penetrating through the first surface, the modified portion of the crystal lattice extending in a plane parallel to the first surface, as a result of the modification, subcritical cracks are formed arranged in a plane parallel to the first surface, a plurality of the subcritical cracks forming a detachment region in the first solid body, the plurality of the subcritical cracks passing at least in some sections through the modified portion of the crystal lattice; and separating the first solid body along the detachment region to form a wafer and a second solid body.Type: GrantFiled: December 9, 2022Date of Patent: May 28, 2024Assignee: Siltectra GmbHInventors: Christian Beyer, Jan Richter
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Patent number: 11997865Abstract: An organic light-emitting display apparatus includes: a substrate; a display unit on the substrate and including a display area and a non-display area outside of the display area; and a thin-film encapsulation layer that seals the display unit, wherein the non-display area includes a dam region located outside of the display area and a plurality of protrusions on at least a part of the display unit outside of the dam region.Type: GrantFiled: June 5, 2023Date of Patent: May 28, 2024Assignee: Samsung Display Co., Ltd.Inventor: Moongon Kim
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Patent number: 11997846Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes an oxide; a first conductor and a second conductor provided apart from each other over the oxide; a third conductor including a region that is over the oxide and overlaps with a region between the first conductor and the second conductor; a first insulator over the third conductor; a fourth conductor that is electrically connected to the first conductor through a first opening provided in the first insulator; a second insulator that is provided over the first insulator and that is provided over the fourth conductor in the first opening; a fifth conductor overlapping with the fourth conductor with the second insulator positioned therebetween in the first opening; and a sixth conductor electrically connected to the second conductor in a second opening provided in the first insulator and the second insulator.Type: GrantFiled: June 27, 2019Date of Patent: May 28, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoru Okamoto, Ryo Tokumaru, Ryota Hodo
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Patent number: 11997867Abstract: A display device includes a first substrate, a plurality of light emitting elements that is provided on the first substrate, a second substrate that is provided so as to face a plurality of the light emitting elements, a wall portion that is provided on the first substrate, surrounds an effective pixel area, and supports the second substrate, and a filling resin layer with which a space surrounded by the first substrate, the second substrate, and the wall portion is filled.Type: GrantFiled: November 12, 2019Date of Patent: May 28, 2024Assignee: SONY CORPORATIONInventors: Hiroshi Fujimaki, Yoshinori Uchida