Patents Examined by Kyoung Lee
  • Patent number: 10980108
    Abstract: A multi-conductor interconnect for a microelectronic device incorporates multiple conductors and integrated shielding for the conductors. The multi-conductor interconnect includes first and second groups of conductors interleaved with one another within a dielectric structure. One of the groups of conductors may be coupled to a reference voltage node to provide shielding for the other group of conductors. The multi-conductor interconnect may further include a shield layer extending over some portion, or all, of the conductors of the first and second groups.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Ping Ping Ooi, Bok Eng Cheah, Jackson Chung Peng Kong, Kooi Chi Ooi
  • Patent number: 10978590
    Abstract: Methods and apparatus to remove epitaxial defects in semiconductors are disclosed. A disclosed example multilayered die structure includes a fin having a first material, where the fin is epitaxially grown from a first substrate layer having a second material, and where a defect portion of the fin is etched or polished. The disclosed example multilayered die structure also includes a second substrate layer having an opening through which the fin extends.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Rishabh Mehandru, Patrick Morrow, Patrick H. Keys
  • Patent number: 10978542
    Abstract: An array substrate, a fabricating method thereof, and a display device are provided. A portion of the array substrate aligned to a secondary function region has a first conductive layer and a second conductive layer disposed on two opposite surfaces of the substrate. A circuit in the second conductive layer is electrically connected to a circuit of a main display region, and a circuit of a driving circuit board is electrically connected to a circuit of the first conductive layer. In this way, a cell on film (COF) is directly placed on a back surface of the substrate, and the main display region and the COF are connected by a passing layer passing through the substrate. No further bending is required.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: April 13, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Kan Wang
  • Patent number: 10978549
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a conductive feature comprising tungsten positioned above the substrate, a coverage layer comprising tungsten nitride positioned on a top surface of the conductive feature, and a plurality of capacitor structures positioned above the substrate.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 13, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 10978582
    Abstract: Disclosed herein are quantum dot devices with patterned gates, as well as related computing devices and methods. For example, a quantum dot device may include gates disposed on a quantum well stack. In some embodiments, the gates may include a first gate with a first length; two second gates with second lengths arranged such that the first gate is disposed between the second gates; and two third gates with third lengths arranged such that the second gates are disposed between the third gates; and the first, second, and third lengths may all be different. In some embodiments, the gates may include a first set of gates alternatingly arranged with a second set of gates, spacers may be disposed between gates of the first set and gates of the second set, and gates in the first or second set may include a gate dielectric having a U-shaped cross-section.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits, James S. Clarke
  • Patent number: 10978358
    Abstract: According to one embodiment, in a processing system and determining method, a X-ray intensity of character X-rays generated by irradiating a catalytic layer of a noble metal formed on a surface of a substrate with X-rays is detected. In the processing system and the determining method, either the detected X-ray intensity or a parameter calculated using the X-ray intensity is obtained as a determination parameter. In the processing system and the determining method, based at least on the determination parameter, whether or not the catalytic layer has been formed into a state suitable for etching the surface of the substrate is determined.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: April 13, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuo Sano, Keiichiro Matsuo, Susumu Obata, Kazuhito Higuchi, Kazuo Shimokawa
  • Patent number: 10971491
    Abstract: A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: April 6, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Yutaka Okazaki
  • Patent number: 10964693
    Abstract: A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 30, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Shigeki Koya, Yasunari Umemoto, Takayuki Tsutsui
  • Patent number: 10964794
    Abstract: A cryogenic semiconductor device includes isolation regions defining an active region having a first P-type ion concentration in a substrate, a gate structure in the substrate, and an ion implantation region having a second P-type ion concentration in the active region below the gate structure, wherein the gate structure includes a gate dielectric layer conformally disposed on inner sidewalls of a gate trench, a lower gate electrode disposed on the gate dielectric layer, and an upper gate electrode disposed on the lower gate electrode, wherein the lower gate electrode has a relatively lower work function than the upper gate electrode.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: March 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Min-Soo Yoo, Sung-Min Park
  • Patent number: 10964816
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Chieh Yang, Li-Yang Chuang, Pei-Yu Wang, Wei Ju Lee, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 10950460
    Abstract: A process is provided in which etched layer(s) are protected from residues or defects caused by or resulting from exposure to atmospheric conditions. Protection is provided through the formation of an encapsulation layer post etch. In one embodiment, the encapsulation is provided by a thin layer formed in an atomic layer deposition (ALD) process. The thin layer prevents the etched layer(s) from exposure to air. This encapsulation process may take place after the etch process thus allowing for substrates to be subsequently exposed to atmospheric conditions with little or no queue time constraints being needed for staging subsequent wet clean processing steps. In one embodiment, the encapsulation process may be performed with no vacuum break between the etch process and the encapsulation process. In one embodiment, the encapsulation film is compatible with subsequent wet process steps and can be removed during this wet process steps without adverse effects.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: March 16, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Angelique Raley, Andrew Metz, Cory Wajda, Junling Sun
  • Patent number: 10950591
    Abstract: Embodiments describe a display integration scheme in which an array of pixel driver chips embedded front side up in an insulator layer. A front side redistribution layer (RDL) spans across and is in electrical connection with the front sides of the array of pixel driver chips, and an array of light emitting diodes (LEDs) is bonded to the front side RDL. The pixel driver chips may be located directly beneath the display area of the display panel.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: March 16, 2021
    Assignee: Apple Inc.
    Inventor: Hsin-Hua Hu
  • Patent number: 10950794
    Abstract: A perovskite thin film and method of forming a perovskite thin film are provided. The perovskite thin film includes a substrate, a hole blocking/electron transport layer, and a sintered perovskite layer. The method of forming the perovskite solar cell includes depositing a perovskite layer onto a substrate and processing (for example, by sintering) the perovskite layer with intense pulsed light to initiate a radiative thermal response that is enabled by an alkyl halide additive.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: March 16, 2021
    Assignee: UNIVERSITY OF LOUISVILLE RESEARCH FOUNDATION, INC.
    Inventors: Thad Druffel, Brandon Lavery, Krishnamraju Ankireddy, Amir Hossein Ghahremani, Blake Martin, Gautam Gupta
  • Patent number: 10940690
    Abstract: The present application relates to a method of manufacturing an ink-jet printhead comprising: providing a silicon substrate (10) including active ejecting elements (11); providing a hydraulic structure layer (20) for defining hydraulic circuits configured to enable a guided flow of ink; providing a silicon orifice plate (30) having a plurality of nozzles (31) for ejection of the ink; assembling the silicon substrate (10) with the hydraulic structure layer (20) and the silicon orifice plate (30); wherein providing the silicon orifice plate (30) comprises: providing a silicon wafer (40) having a planar extension delimited by a first surface (41) and a second surface (42) on opposite sides of the silicon wafer (40); performing a thinning step at the second surface (42) so as to remove from the second surface (42) a central portion (43) having a preset height (H), the silicon wafer (40) being formed, following the thinning step, by a base portion (44) having a planar extension and a peripheral portion (45) extend
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: March 9, 2021
    Assignee: SICPA HOLDING SA
    Inventors: Lucia Giovanola, Silvia Baldi, Anna Merialdo, Paolo Schina
  • Patent number: 10943891
    Abstract: A semiconductor module includes a base plate for dissipating heat and a body having a bottom surface facing the base plate, a top surface opposite the bottom surface, and side surfaces between the bottom and top surfaces, wherein a first main electrode through which a first main current flows faces a first side surface among the side surfaces, and a second main electrode through which a second main current flows faces a second side surface opposite the first side surface. A power conversion apparatus includes a plurality of the semiconductor modules, wherein a cylindrical section is formed by arranging the semiconductor modules to surround a predetermined position, some of the first and second main electrodes are arranged on a first ring-shaped end surface at one end of the cylindrical section, and remaining electrodes are arranged on a second ring-shaped end surface at another end of the cylindrical section.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: March 9, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yuji Sano
  • Patent number: 10943895
    Abstract: A method of assembling a plurality of linear arrays from a silicon wafer having a first surface and a second surface opposite the first surface, the first surface having at least a first linear array of sensor/emitter elements and a second linear array of sensor/emitter elements, each arranged parallel relative to a first direction, and a sacrificial portion positioned between the first linear array of sensor/emitter elements and the second linear array of sensor/emitter elements.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: March 9, 2021
    Assignee: Xerox Corporation
    Inventors: Gary D. Redding, Joseph F. Casey
  • Patent number: 10937858
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes: providing a substrate including an electrical component; forming a capacitor structure in the substrate, proximal to a heterogeneous interface of the substrate, and physically and electrically isolated from the electrical component; forming a conductive terminal over and electrically connected with the capacitor structure; and contacting the conductive terminal with a probe to measure an electrical parameter of the capacitor structure, wherein the electrical parameter corresponds to a humidity permeability at the heterogeneous interface. A semiconductor structure thereof is also provided.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yang-Che Chen, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
  • Patent number: 10937725
    Abstract: A semiconductor device comprises: a ceramic substrate having conductor layers on both surfaces thereof; a semiconductor element joined to the upper surface conductor layer of the ceramic substrate; a frame member arranged on the upper surface conductor layer so as to surround a side surface of the semiconductor element; and an electrode, which is joined to an upper portion of the semiconductor element via a second fixing layer, and has fitting portions on a side surface of the electrode. On an inner wall of the frame member, fitting portions to be fitted to the fitting portions of the electrode and four positioning portions extending from the inner wall of the frame member to the side surfaces of the electrode are formed.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: March 2, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuya Muramatsu, Noriyuki Besshi, Ryuichi Ishii
  • Patent number: 10937978
    Abstract: A perovskite thin film and method of forming a perovskite thin film are provided. The perovskite thin film includes a substrate, a hole blocking/electron transport layer, and a sintered perovskite layer. The method of forming the perovskite solar cell includes depositing a perovskite layer onto a substrate and sintering the perovskite layer with intense pulsed light.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: March 2, 2021
    Assignee: UNIVERSITY OF LOUISVILLE RESEARCH FOUNDATION, INC.
    Inventors: Thad Druffel, Brandon Lavery
  • Patent number: 10937816
    Abstract: A switching element, a manufacturing method thereof, an array substrate and a display device are provided. The switching element includes: a base substrate; a first thin-film transistor (TFT), disposed on the base substrate; and a second TFT, disposed on the first TFT, wherein the first TFT includes a first electrode and a second electrode, and the first TFT and the second TFT share the first electrode and the second electrode.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: March 2, 2021
    Assignees: Hefei BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Liqing Liao, Hongmin Li, Ying Wang, Dong Wang