Patents Examined by Kyoung Lee
  • Patent number: 12009282
    Abstract: A memory device includes: a wiring substrate including a multilevel wiring layer and first and second surfaces at opposite sides; a control element embedded in the wiring substrate and having first and second element surfaces at opposite sides, with multiple electrode pads connected to the multilevel wiring layer at the first element surface; a first heat dissipation member at a region of the first surface overlapping the control element; a heat dissipation structure facing the second element surface and exposed at the second surface; and at least one memory element connected with the multilevel wiring layer at a first surface region not overlapping the control element. The multilevel wiring layer includes a signal pattern electrically connecting the control element with the memory element or the external connection terminal, and a heat dissipation conductor pattern forming a heat dissipation path between the control element and the first heat dissipation member.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: June 11, 2024
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventor: Shuzo Akejima
  • Patent number: 12009792
    Abstract: Example embodiments relate to power amplifiers with decreased RF return current losses. One embodiment includes a RF power amplifier package that includes a semiconductor die, an input lead, first bondwire connections, second bondwire connections, and a plurality of shields. The semiconductor die includes an RF power transistor that includes output bond pads, input bond pads, a plurality of input fingers, and a plurality of output fingers. Further, each shield of the plurality of shields is arranged in between a respective input finger of the plurality of input fingers and a respective output finger of the plurality of output fingers and extending along with said respective input finger and output finger. In addition, each shield of the plurality of shields is connected to a ground terminal of the RF power transistor. The input fingers, output fingers, and shields are formed using a metal layer stack of multiple metal layers.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: June 11, 2024
    Assignee: Ampleon Netherlands B.V.
    Inventors: Vittorio Cuoco, Jos Van Der Zanden, Yi Zhu, Iouri Volokhine
  • Patent number: 12009201
    Abstract: There is provided a technique, including: (a) forming NH termination on a surface of a substrate by supplying a first reactant containing N and H to the substrate; (b) forming a first SiN layer having SiCl termination formed on its surface by supplying SiCl4 as a precursor to the substrate to react the NH termination formed on the surface of the substrate with the SiCl4; (c) forming a second SiN layer having NH termination formed on its surface by supplying a second reactant containing N and H to the substrate to react the SiCl termination formed on the surface of the first SiN layer with the second reactant; and (d) forming a SiN film on the substrate by performing a cycle a predetermined number of times under a condition where the SiCl4 is not gas-phase decomposed after performing (a), the cycle including non-simultaneously performing (b) and (c).
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: June 11, 2024
    Assignee: Kokusai Electric Corporation
    Inventors: Katsuyoshi Harada, Tatsuru Matsuoka, Yoshitomo Hashimoto
  • Patent number: 11997846
    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes an oxide; a first conductor and a second conductor provided apart from each other over the oxide; a third conductor including a region that is over the oxide and overlaps with a region between the first conductor and the second conductor; a first insulator over the third conductor; a fourth conductor that is electrically connected to the first conductor through a first opening provided in the first insulator; a second insulator that is provided over the first insulator and that is provided over the fourth conductor in the first opening; a fifth conductor overlapping with the fourth conductor with the second insulator positioned therebetween in the first opening; and a sixth conductor electrically connected to the second conductor in a second opening provided in the first insulator and the second insulator.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 28, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoru Okamoto, Ryo Tokumaru, Ryota Hodo
  • Patent number: 11997865
    Abstract: An organic light-emitting display apparatus includes: a substrate; a display unit on the substrate and including a display area and a non-display area outside of the display area; and a thin-film encapsulation layer that seals the display unit, wherein the non-display area includes a dam region located outside of the display area and a plurality of protrusions on at least a part of the display unit outside of the dam region.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: May 28, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventor: Moongon Kim
  • Patent number: 11997909
    Abstract: The present disclosure relates to a display device including an optical device, more specifically, it relates to a display device in which the optical device is positioned under the display panel so that the optical device is not exposed in the front direction. Even if the optical device is located under the display panel, the display device can normally perform the function of the optical device related to the front direction of the display panel and have a structure for this.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: May 28, 2024
    Assignee: LG Display Co., Ltd.
    Inventors: JongHee Hwang, KiDuk Kim
  • Patent number: 11996331
    Abstract: A method for separating a solid body includes: providing a first solid body having opposite first and second surfaces and a crystal lattice, and that is at least partially transparent to a laser beam emitted by a laser; modifying a portion of the crystal lattice by the laser beam, the laser beam penetrating through the first surface, the modified portion of the crystal lattice extending in a plane parallel to the first surface, as a result of the modification, subcritical cracks are formed arranged in a plane parallel to the first surface, a plurality of the subcritical cracks forming a detachment region in the first solid body, the plurality of the subcritical cracks passing at least in some sections through the modified portion of the crystal lattice; and separating the first solid body along the detachment region to form a wafer and a second solid body.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: May 28, 2024
    Assignee: Siltectra GmbH
    Inventors: Christian Beyer, Jan Richter
  • Patent number: 11997867
    Abstract: A display device includes a first substrate, a plurality of light emitting elements that is provided on the first substrate, a second substrate that is provided so as to face a plurality of the light emitting elements, a wall portion that is provided on the first substrate, surrounds an effective pixel area, and supports the second substrate, and a filling resin layer with which a space surrounded by the first substrate, the second substrate, and the wall portion is filled.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: May 28, 2024
    Assignee: SONY CORPORATION
    Inventors: Hiroshi Fujimaki, Yoshinori Uchida
  • Patent number: 11996345
    Abstract: A package structure includes a first semiconductor die, a first insulating encapsulation, a thermal coupling structure, and a heat dissipating component thermally coupled to the first semiconductor die through the thermal coupling structure. The first semiconductor die includes an active side, a rear side, and a sidewall connected to the active side and the rear side. The first insulating encapsulation extends along the sidewall of the first semiconductor die and includes a first side substantially leveled with the active side, a second side opposite to the first side, and topographic features at the second side. The thermal coupling structure includes a metallic layer overlying and the rear side of the first semiconductor die and the topographic features of the first insulating encapsulation. A manufacturing method of a package structure is also provided.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11996375
    Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu, Kun-Tong Tsai, Hung-Chih Chen
  • Patent number: 11990449
    Abstract: Embodiments include a semiconductor package, a package on package system, and a method of forming the semiconductor package. The semiconductor package includes a first redistribution layer, a stack of dies on the first redistribution layer, a second redistribution layer over the stack of dies and the first redistribution layer, and a plurality of interconnects coupled to the stack of dies and the first and second redistribution layers. The interconnects may extend substantially vertical from a top surface of the first redistribution layer to a bottom surface of the second redistribution layer. The semiconductor package may also include a mold layer between the first redistribution layer and the second redistribution layer. The plurality of interconnects may be through mold vertical wire interconnects. The first and second redistribution layers may be dual-sided redistribution layers. The semiconductor package may further include adhesive layers coupled to the stack of dies.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventor: Hyoung Il Kim
  • Patent number: 11991874
    Abstract: A semiconductor structure includes a substrate, a bit line, and a first isolation layer. A groove is set in the substrate. A bottom end of the bit line is set in the groove. The first isolation layer is at least partially set on a sidewall of the bit line, and the first isolation layer is in direct contact with the bit line.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: May 21, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Longyang Chen, Gongyi Wu
  • Patent number: 11991907
    Abstract: The disclosure provides a display panel and a display device, including a display cell. The display cell includes: a plurality of display pins and a plurality of cell test pins, which are arranged in a bonding region of the display cell; and a chip on film bonded to a side facing away from a display surface of the display cell. An orthographic projection of the chip on film on the display cell completely covers the display pins and the cell test pins.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: May 21, 2024
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xiaoxia Huang, Bing Ji, Shuang Zhang
  • Patent number: 11990336
    Abstract: To provide a silicon epitaxial wafer production method and a silicon epitaxial wafer in which the DIC defects can be suppressed, a silicon epitaxial wafer production method is provided, in which an epitaxial layer is grown in a vapor phase on a principal plane of a silicon single crystal wafer. The principal plane is a {110} plane or a plane having an off-angle of less than 1 degree from the {110} plane. The silicon epitaxial wafer production method includes setting a temperature of the silicon single crystal wafer to 1100° C. to 1135° C. and growing the epitaxial layer in the vapor phase at a growth rate of 2.0 ?m/min to 3.0 ?m/min.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 21, 2024
    Assignee: SUMCO CORPORATION
    Inventors: Masayuki Ishibashi, Midori Yoshida, Daisuke Maruoka
  • Patent number: 11985873
    Abstract: A display device includes: a display area having a plurality of sub-pixels; a plurality of pad electrodes in a peripheral area outside the display area; a first organic insulating layer comprising an opening overlapping the plurality of pad electrodes; and an integrated circuit overlapping the plurality of pad electrodes and electrically connected to the plurality of pad electrodes, wherein a distance between an edge of the first organic insulating layer defining the opening and an edge of the integrated circuit is 40 micrometers (?m) or more.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: May 14, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dongyoub Lee, Heejin Kim, Kitae Kim, Juhyun Shin
  • Patent number: 11984409
    Abstract: A photoelectric conversion panel includes a thin-film transistor provided in a first region, a photoelectric conversion element provided in the first region, a first organic film having a first groove portion provided in a second region, a second organic film having a second groove portion provided in the second region and in a position different from that of the first groove portion, a first inorganic film formed so as to cover the first organic film and cover an inner surface of the first groove portion, and a second inorganic film formed so as to cover the second organic film and cover an inner surface of the second groove portion.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: May 14, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Fumiki Nakano, Makoto Nakazawa, Hiroyuki Moriwaki, Rikiya Takita
  • Patent number: 11985850
    Abstract: A display module and a display apparatus, the display apparatus implementing grounding of a support planarization layer (300) by means of at least one of a grounded first heat dissipation layer (400) and second heat dissipation layer (500) being electrically connected to the support planarization layer (300), so that the grounded support planarization layer (300) does not interfere with touch control signals in the display module, improving the touch control performance of the display module.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: May 14, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Meiling Gao, Yonghong Zhou
  • Patent number: 11984434
    Abstract: A display device includes a display panel and a light unit. The light unit includes a substrate, a circuit layer disposed on the substrate and including a line, an insulation layer covering the circuit layer, light emitting elements including a first electrode, a second electrode, and a light emitting layer, and a conductive layer electrically connected to one of the first electrode and the second electrode to cover at least a portion of the line.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: May 14, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Duk-Sung Kim, Junghyun Kwon, Dong-Yoon Kim
  • Patent number: 11983340
    Abstract: A display substrate is provided. The display substrate includes: a base substrate; a pixel defining layer disposed on the base substrate, wherein the pixel defining layer defines a plurality of sub-pixel areas and has a groove therein; and a touch structure disposed in the groove, wherein the touch structure is configured to provide a touch function.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: May 14, 2024
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Zhaowei Yu, Qinhe Wei, Rongjian Yan, Wenbin Chen
  • Patent number: 11980070
    Abstract: A display panel has a display region and at least one bonding region located beside the display region. The display panel includes: a base; and a plurality of conductive pads provided on the base and located in each bonding region. The plurality of conductive pads are arranged at intervals along a first direction. The plurality of conductive pads include at least one first type of conductive pad configured to transmit a direct current voltage signal to the display region and a plurality of second type of conductive pads configured to transmit a pulse voltage signal to the display region. A dimension of one first type of conductive pad in the first direction is greater than a dimension of one second type of conductive pad in the first direction.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: May 7, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Bing Zhang, Shanghong Li, Mengyue Fan