Abstract: In-package radio frequency (RF) waveguides as high bandwidth chip-to-chip interconnects and methods for using the same are disclosed. In one example, an electronic package includes a package substrate, first and second silicon dies or tiles, and an RF waveguide. The first and second silicon dies or tiles are attached to the package substrate. The RF waveguide is formed in the package substrate and interconnects the first silicon die or tile with the second silicon die or tile.

Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

Abstract: An optoelectronic device package includes a first redistribution layer (RDL), a first electronic die disposed over the first RDL, wherein an active surface of the first electronic die faces the first RDL. The optoelectronic device package further includes a second electronic die disposed over the first RDL, and a photonic die disposed over and electrically connected to the second electronic die. An active surface of the second electronic die is opposite to the first RDL.

Abstract: A display apparatus includes a base substrate, a polysilicon active pattern disposed on the base substrate, including polycrystalline silicon, including a source region and a drain region each doped with impurities and a channel region between the source region and the drain region, and including indium, a first gate electrode overlapping the channel region, and a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region.

Abstract: A flexible display panel and a manufacturing method thereof, and a flexible display apparatus are disclosed. The flexible display panel includes: a flexible substrate, the flexible substrate including a display area, a peripheral area, a welding area and a bending area, and the bending area including a first edge; and the flexible display panel further includes: a barrier and an organic insulation layer, wherein the peripheral area includes a peripheral transition area between the bending area and the display area, the organic insulation layer in the peripheral transition area is provided with a first groove, the first groove is on one side of the barrier and extends along a direction substantially parallel to a bending axis, and the first groove is on one side of the first edge proximal to the display area.

Abstract: A bendable display device includes a display panel, a display circuit board having a first end thereof electrically connected to the display panel, a touch circuit board having a first end thereof electrically connected to the display panel, a support layer disposed on a surface of the display panel, and first and second heat dissipation layers. Each of the first heat dissipation layer and the second heat dissipation layer is disposed on a side of the support layer away from the display panel, and the first dissipation layer and the second dissipation layer are disposed on two sides of a bending area of the bendable display device. A second end of the display circuit board and a second end of the touch circuit board are respectively disposed on the first heat dissipation layer and the second heat dissipation layer.

Abstract: An electronic modulating device is provided. The electronic modulating device includes a first modulating unit. The first modulating unit includes a first transistor including a channel arranged in an extending direction. The first modulating unit also includes a first modulating electrode electrically connected to the first transistor and arranged in a first longitudinal direction. The electronic modulating device also includes a second modulating unit. The second modulating unit includes a second transistor including a channel arranged in the extending direction. The second modulating unit also includes a second modulating electrode electrically connected to the second transistor and arranged in a second longitudinal direction that is different from the first longitudinal direction. The first included angle between the extending direction and the first longitudinal direction is different from a second included angle between the extending direction and the second longitudinal direction.

Abstract: A display apparatus includes a first substrate, a second substrate, and a transistor. The first transistor includes a polymer resin. The second substrate is arranged between the first substrate and the transistor and includes a glass material. A liquidus temperature of the glass material is less than 1000° C. The transistor overlaps at least one of the first substrate and the second substrate and includes a semiconductor layer.

Abstract: A power module is provided and includes first stack, second stack, and third stacks of layers, a heat pipe, and at least one cold plate or heat sink. The third stack of layers is disposed between the first and second stacks of layers and includes a first semiconductor die, a second semiconductor die and a center spacer layer disposed between the first semiconductor die and the second semiconductor die. The heat pipe extends at least partially into the center spacer layer. The at least one cold plate or heat sink receives thermal energy from the first stack of layers and the second stack of layers. The first stack of layers, the second stack of layers, the third stack of layers, the heat pipe and the at least one cold plate or heat sink facilitate dual sided cooling of each of the first semiconductor die and the second semiconductor die.

Abstract: A display panel includes an upper substrate to which external light is incident, a sealing member which is in a non-display area and couples the upper substrate to a lower display substrate. The upper display substrate includes: a base substrate; a light shielding layer and filter layer each corresponding to the non-display area and absorbing a portion of external light which is transmitted through the base substrate at the non-display area, the filter layer and the light shielding layer having different colors from each other. In a first non-display area of the base substrate which corresponds to the sealing member, only one among the filter layer and the light shielding layer is disposed. In a second non-display area of the base substrate which is adjacent to the first non-display area, both the filter layer and the light shielding layer are disposed.

Abstract: Provided is a tiled display device. The tiled display device includes adjacent first and second display devices including a display area having pixels, a bonding area between the display areas of the first and second display devices, data lines extending in a first direction, first gate lines extending in the first direction, and configured to transmit a gate signal, and off voltage lines extending in the first direction, and configured to transmit an off voltage, wherein one of the off voltage lines is between a first pixel at an outermost side of the first display device and a second pixel located more inwardly than first pixel, and wherein the off voltage lines are not between a third pixel at an outermost side of the second display device and the first pixel.

Abstract: An improved memory module and methods for constructing the same are disclosed herein. The memory module includes a substrate having a first surface and a second surface opposite the first surface, each having a central portion, a first array area and a second array area. The first array area is cooler than the second array area during operation. The memory module also includes a power management integrated circuit attached to the central portion of the first surface. The memory module also includes a first semiconductor die attached to the substrate in the first array area. The first semiconductor die has a first performance rating of an operating parameter at high temperatures. The memory module also includes a second semiconductor die attached to the substrate in the second array area. The second semiconductor die has a second performance rating of an operating parameter better than the first performance rating at high temperatures.

Abstract: A display device includes a first substrate that includes a first electrode, a second substrate disposed under the first substrate and that includes, a second electrode that overlaps the first electrode, and an anisotropic conductive film disposed between the first substrate and the second substrate. The anisotropic conductive film includes an insulating resin layer and a plurality of conductive particles in the insulating resin layer. The conductive particles include first conductive particles that overlap the first electrode and the second electrode, and second conductive particles other than the first conductive particles. Each of the first conductive particles and the second conductive particles includes a first flat surface, a second flat surface that faces the first flat surface, and a curved surface rounded between the first flat surface and the second flat surface.

Abstract: Embodiments of the present disclosure provide a display panel, including: a display substrate, wherein the display substrate includes a display area and a bezel area arranged around a periphery of the display area, the bezel area including a first area arranged around the periphery of the display area, and a second area arranged around a periphery of the first area; and the display substrate further includes a plurality of electrical functional layers located at different levels respectively and at least part of film layers therein being partially superposed; wherein at least part of the electrical functional layers are distributed in the display area, and at least part of the electrical functional layers are distributed in the first area and the second area, the first area having a higher light transmittance than the second area and the display area.

Abstract: The display device includes a substrate, a transistor, a leveling film, a display element, a partition wall, and at least one dam. The substrate has a display region and a peripheral region surrounding the display region. The transistor is located over the display region. The leveling film is located over the display region and covers the transistor. The display element is located over the leveling film and includes a pixel electrode electrically connected to the transistor. The partition wall covers an edge portion of the pixel electrode. The at least one dam is located over the peripheral region, is spaced away from the leveling film, and surrounds the display region. The at least one dam has a base and stopper. The base includes a material included in at least one of the leveling film and the partition wall.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a first fin, and the first fin has a channel region and a source/drain region. The method includes forming a stack structure over the first fin, and the stack structure includes a first semiconductor layer and a second semiconductor layer vertically stacked over the fin. The method also includes removing a portion of the second semiconductor layer in the channel region, and a portion of the first semiconductor layer is remaining in the channel region. The method further includes forming a cladding layer over the remaining first semiconductor material layer in the channel region to form a nanostructure, wherein the nanostructure has a dumbbell shape. The method includes forming a gate structure surrounding the nanostructure.

Abstract: A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.