Patents Examined by Lan Vinh
  • Patent number: 11069568
    Abstract: In one embodiment, a method of forming a barrier layer is provided. The method includes positioning a substrate in a processing chamber, forming a barrier layer over the substrate and in contact with the underlayer, and annealing the substrate. The substrate comprises at least one underlayer having cobalt, tungsten, or copper. The barrier layer has a thickness of less than 70 angstroms.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: July 20, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Susmit Singha Roy, Yihong Chen, Abhijit Basu Mallick, Srinivas Gandikota
  • Patent number: 11062881
    Abstract: A plasma etching method according to an exemplary embodiment comprises arranging a substrate on an electrostatic chuck in a region surrounded by a focus ring. The substrate, in a state of being held by the electrostatic chuck, is etched by means of ions from a plasma. The electrostatic chuck includes a plurality of electrodes including a first electrode and a second electrode. The first electrode extends under a central region of the substrate. The second electrode extends under an edge region of the substrate. A plurality of voltages are respectively applied to the plurality of electrodes, wherein the plurality of voltages are determined such that, in the state in which the substrate is held by the electrostatic chuck, the ions from the plasma are incident on both the central region and the edge region substantially vertically.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: July 13, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masayuki Sawataishi, Jun Hirose
  • Patent number: 11049756
    Abstract: Etch uniformity is improved by providing a thermal pad between an insert ring and electrostatic chuck in an etching chamber. The thermal pad provides a continuous passive heat path to dissipate heat from the insert ring and wafer edge to the electrostatic chuck. The thermal pad helps to keep the temperature of the various components in contact with or near the wafer at a more consistent temperature. Because temperature may affect etch rate, such as with etching hard masks over dummy gate formations, a more consistent etch rate is attained. The thermal pad also provides for etch rate uniformity across the whole wafer and not just at the edge. The thermal pad may be used in an etch process to perform gate replacement by removing hard mask layer(s) over a dummy gate electrode.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Huei Chiu, Tsung Fan Yin, Chen-Yi Liu, Hua-Li Hung, Xi-Zong Chen, Yi-Wei Chiu
  • Patent number: 11042091
    Abstract: The present invention relates to a composition comprising; components a. c. and d; and optional component b. wherein, component a. is a metal compound having the structure (I), optional component b., is a polyol additive, having structure (VI), component c. is a high performance polymer additive, and component d. is a solvent. The present invention further relates to using this compositions in methods for manufacturing electronic devices through either the formation of a patterned films of high K material comprised of a metal oxide on a semiconductor substrate, or through the formation of patterned metal oxide comprised layer overlaying a semiconductor substrate which may be used to selectively etch the semiconductor substrate with a fluorine plasma.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: June 22, 2021
    Assignee: Merck Patent GmbH
    Inventors: Huirong Yao, JoonYeon Cho, M. Dalil Rahman
  • Patent number: 11028321
    Abstract: An etching composition is provided. The etching composition includes phosphoric acid, phosphoric anhydride, a silane compound represented by Formula 1 below and water: wherein R1 to R6 are independently hydrogen, halogen, a substituted or unsubstituted C1-C20 hydrocarbyl group, a C1-C20 alkoxy group, a carboxy group, a carbonyl group, a nitro group, a tri(C1-C20-alkyl)silyl group, a phosphoryl group, or a cyano group. L is a direct bond or C1 to C3 hydrocarbylene, and A is an n-valent radical, while n is an integer of 1 to 4.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: June 8, 2021
    Assignees: SK Innovation Co., Ltd., SK-Materials Co., Ltd.
    Inventors: Cheol Woo Kim, Yu Na Shim, Kwang Kuk Lee, Jae Hoon Kwak, Young Bom Kim, Jong Ho Lee, Jin Kyung Jo
  • Patent number: 11018015
    Abstract: The invention provides: a composition for forming an organic film, the composition having high filterability and enabling formation of an organic film which has high pattern-curving resistance, and which prevents a high-aspect line pattern particularly finer than 40 nm from line collapse and twisting after dry etching; a method for forming an organic film and a patterning process which use the composition; and a substrate for manufacturing a semiconductor device, including the organic film formed on the substrate. The composition for forming an organic film includes a condensate (A), which is a condensation product of dihydroxynaphthalene shown by the following formula (1) and a condensation agent, or a derivative of the condensate (A). A sulfur content among constituent elements contained in the condensate (A) or the derivative of the condensate (A) is 100 ppm or less in terms of mass.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: May 25, 2021
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tsutomu Ogihara, Daisuke Kori, Seiichiro Tachibana, Yusuke Biyajima, Naoki Kobayashi, Kazumi Noda
  • Patent number: 11017987
    Abstract: An etching method includes inputting, to a setting unit, at least electric power, a pressure, and a gas flow rate, performing etching processing in a chamber, on the basis of a value inputted to the setting unit, and calculating an ion energy distribution mathematical function, by using a measured value upon the etching processing.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: May 25, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Masanaga Fukasawa
  • Patent number: 11008482
    Abstract: The present invention relates to a polishing composition, and more particularly, to a chemical mechanical polishing (CMP) composition used to chemically and mechanically polish a semiconductor wafer. The polishing composition of the present invention, by comprising anion-modified silica polishing particles in which the zeta potential (?) is ??10 mV, can exhibit excellent polishing performance, and more specifically, which can achieve a high polishing rate with respect to an indium-containing polishing substrate, while improving the dispersibility of the composition and reducing residual defects on the substrate.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 18, 2021
    Inventors: Hye Kyung So, Myeong Hoon Han
  • Patent number: 11011387
    Abstract: A subtractive forming method that includes providing a material stack including a samarium and selenium containing layer and an aluminum containing layer in direct contact with the samarium and selenium containing layer. The samarium component of the samarium and selenium containing layer of the exposed portion of the material stack is etched with an etch chemistry comprising citric acid and hydrogen peroxide that is selective to the aluminum containing layer. The hydrogen peroxide reacts with the aluminum containing layer to provide an oxide etch protectant surface on the aluminum containing layer, and the citric acid etches samarium selectively to the oxide etch protectant surface. Thereafter, a remaining selenium component of is removed by elevating a temperature of the selenium component.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: May 18, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christine Armstrong, Matthew W. Copel, Yu Luo, Paul M. Solomon
  • Patent number: 10995268
    Abstract: A silicon nitride etching composition effective to selectively etch a silicon nitride film contains an inorganic acid; a silicon-based compound; from 0.01 to 1 wt%, based on total weight of the etching composition, of an ammonium-based compound composed of ammonium acetic acid; and water. The silicon-based compound may be represented by Chemical Formula 1 below or Chemical Formula 2 below, (R1)3-Si-R2-Si-(R1)3??Chemical Formula 1, (R3)3-Si-R4-Si-(R3)3??Chemicl Formula 2. A method of etching a silicon nitride film includes providing the etching composition; and wet etching the silicon nitride film in the etching composition at an etching rate that is at least 200 times faster than a corresponding silicon oxide film.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: May 4, 2021
    Assignee: LTCAM CO., LTD.
    Inventors: Sok Ho Lee, Jung Hwan Song, Seong Sik Jeon, Sung Il Jo, Byeoung Tak Kim, Ah Hyeon Lim, Junwoo Lee
  • Patent number: 10995238
    Abstract: A neutral to alkaline chemical mechanical composition for polishing tungsten includes, as initial components: water; an oxidizing agent selected from an iodate compound, a periodate compound and mixtures thereof; colloidal silica abrasive particles including a nitrogen-containing compound; optionally, a pH adjusting agent; and, optionally, a biocide. The chemical mechanical polishing method includes providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the neutral to alkaline chemical mechanical polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the tungsten is polished away from the substrate and, further, to at least inhibit static etch of the tungsten.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: May 4, 2021
    Assignee: Rohm and Haas Electronic Materials CMP Holdings
    Inventors: Yi Guo, Tony Quan Tran
  • Patent number: 10982335
    Abstract: A method for improving both the microscopic and macroscopic uniformity of materials during etching is disclosed herein. These improvements may be accomplished through the formation and dissolution of thin, self-limiting layers on the material surface by the use of wet atomic layer etching (ALE) techniques. For etching of polycrystalline materials, these self-limiting reactions can be used to prevent this roughening of the surface during etching. Thus, as disclosed herein, a wet ALE process uses sequential, self-limiting reactions to first modify the surface layer of a material and then selectively remove the modified layer.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 20, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Paul Abel
  • Patent number: 10982144
    Abstract: Provided are a silicon nitride layer etching composition, and more specifically, a silicon nitride layer etching composition, capable of etching the silicon nitride layer at a high selectivity ratio relative to a silicon oxide layer by comprising a polysilicon compound in the etching composition, an etching method of a silicon nitride layer using the same, and a method of manufacturing a semiconductor device.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: April 20, 2021
    Assignee: ENF TECHNOLOGY CO., LTD.
    Inventors: Dong Hyun Kim, Hyeon Woo Park, Jang Woo Cho, Tae Ho Kim, Myung Ho Lee, Myung Geun Song
  • Patent number: 10983075
    Abstract: The present application relates to a scanning probe microscope comprising a probe arrangement for analyzing at least one defect of a photolithographic mask or of a wafer, wherein the scanning probe microscope comprises: (a) at least one first probe embodied to analyze the at least one defect; (b) means for producing at least one mark, by use of which the position of the at least one defect is indicated on the mask or on the wafer; and (c) wherein the mark is embodied in such a way that it may be detected by a scanning particle beam microscope.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: April 20, 2021
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Gabriel Baralia, Christof Baur, Klaus Edinger, Thorsten Hofmann, Michael Budach
  • Patent number: 10971369
    Abstract: In cycle etching in which a depo process and an etching process are repeated, a depo film thickness over a pattern is controlled precisely, and etching is executed to have a desired shape stably for a long time.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 6, 2021
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Miyako Matsui, Tatehito Usui, Masaru Izawa, Kenichi Kuwahara
  • Patent number: 10969379
    Abstract: A bioelectrochemical sensor utilizing a nanoporous gold electrode. The bioelectrochemical sensor is suitable for measuring redox in biologic media while having increased resistance to biofouling as compared to conventional electrodes such as planar gold electrodes, due to greater exposed surface area of the three-dimensional ligature structure defining the nanopores. The nanopores have a pore size of 5-100 nm, preferably with an average pore size of less than 50 nm, and more preferably with an average pore size of less than 20 nm.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: April 6, 2021
    Assignees: THE REGENTS OF THE UNIVERSITY OF MICHIGAN, Virginia Commonwealth University
    Inventors: Rodney C. Daniels, Kevin R. Ward, Maryanne M. Collinson
  • Patent number: 10971364
    Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of boron-carbon films on a substrate. In one implementation, a method of processing a substrate is provided. The method comprises flowing a hydrocarbon-containing gas mixture into a processing volume of a processing chamber having a substrate positioned therein, wherein the substrate is heated to a substrate temperature from about 400 degrees Celsius to about 700 degrees Celsius, flowing a boron-containing gas mixture into the processing volume and generating an RF plasma in the processing volume to deposit a boron-carbon film on the heated substrate, wherein the boron-carbon film has an elastic modulus of from about 200 to about 400 GPa and a stress from about ?100 MPa to about 100 MPa.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: April 6, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Prashant Kumar Kulshreshtha, Ziqing Duan, Karthik Thimmavajjula Narasimha, Kwangduk Douglas Lee, Bok Hoen Kim
  • Patent number: 10964546
    Abstract: There is provided a substrate processing method which is capable of suitably etching a boron-doped silicon. According to the present invention, a wafer W including an SiB layer made of boron-doped silicon is exposed to a fluorine gas and an ammonia gas, and the wafer W mounted on a stage is heated.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: March 30, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Reiko Sasahara, Tsuhung Huang, Teppei Okumura
  • Patent number: 10964549
    Abstract: A wafer is polished by performing a chemical reaction to change a property of a first portion of a material layer on the wafer using a first chemical substance. A first rinse is performed to remove the first chemical substance and retard the chemical reaction. A mechanical polishing process is then performed to remove the first portion of the material layer.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Shen-Nan Lee, Teng-Chun Tsai, Chu-An Lee, Chen-Hao Wu, Chun-Hung Liao, Huang-Lin Chao
  • Patent number: 10957551
    Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Yuan Tseng, Wei-Liang Lin, Hsin-Chih Chen, Shi Ning Ju, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Liu