Abstract: A nonvolatile memory module may include a nonvolatile memory device, a nonvolatile memory controller configured to control the nonvolatile memory device, a volatile memory device configured as a cache memory of the nonvolatile memory device, and a module controller configured to receive a command and an address from an external device, external to the nonvolatile memory module, and to send a volatile memory command and a volatile memory address to the volatile memory device through a first bus and a nonvolatile memory command and a nonvolatile memory address to the controller through a second bus in response to the received command and address. The volatile memory device is configured to load two or more cache data on each of two or more memory data line groups and two or more tags on each of two or more tag data line groups in response to the volatile memory address.

Abstract: A nonvolatile memory device may include a nonvolatile memory device may include a nonvolatile memory cell array; a peripheral circuit suitable for: activating an operation voltage in response to an operation voltage activation command, performing an operation to the nonvolatile memory cell array using the activated operation voltage in response to an operation command, and deactivating the activated operation voltage in response to an operation voltage deactivation command after the performing of the operation; and a control circuit suitable for controlling the peripheral circuit to execute an intervening operation during the activating of the operation voltage, the performing of the operation, and the deactivating of the activated operation voltage.

Abstract: A computer memory system, delay calibration circuit, and method of operating a delay calibration circuit are provided. The disclosed method includes providing a delay-line ring oscillator on silicon of a chip, providing at least one counter on the silicon of the chip, and measuring a chip-specific delay for performing an operation with the chip by synchronizing the at least one counter and operation of the delay-line ring oscillator with a timing trigger.

Abstract: An apparatus includes a clock terminal configured to receive an external clock signal, a clock generator configured to generate an internal clock signal in response to the external clock signal, first and second output circuits each coupled to the clock generator, a first clock line coupled between the clock generator and the first output circuit, and the second clock line coupled between the clock generator and the second output circuit. The first clock line represents a first capacitance and a first resistance while the second clock line represents a second capacitance and a second resistance. A first value defined as the product of the first capacitance and the first resistance is substantially equal to a second value defined as the product of the second capacitance and the second resistance.

Abstract: The present disclosure includes apparatuses and methods for in data path compute operations. An example apparatus includes an array of memory cells. Sensing circuitry is selectably coupled to the array. A plurality of shared input/output (I/O) lines provides a data path. The plurality of shared I/O lines selectably couples a first subrow of a row of the array via the sensing circuitry to a first compute component in the data path to move a first data value from the first subrow to the first compute component and a second subrow of the respective row via the sensing circuitry to a second compute component to move a second data value from the second subrow to the second compute component. An operation is performed on the first data value from the first subrow using the first compute component substantially simultaneously with movement of the second data value from the second subrow to the second compute component.

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might also include a controller configured to cause sensing circuitry to iterate through a plurality of first elements and a plurality of second elements via a loop structure to perform an operation using the plurality of first elements and the plurality of second elements, wherein a conditional statement associated with the loop structure is used to determine whether at least one of a plurality of bits stored as an iterator mask has a particular bit-value. An example apparatus might also include sensing circuitry controllable to perform a shift operation using the iterator mask at each iteration of the loop structure and perform an AND operation using the iterator mask at each iteration of the loop structure.

Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.

Abstract: In some embodiments, a system includes a memory testing circuit configured to perform a test to determine whether a portion of a memory is operational at a specified amount of time after a power-up request by performing operations. The operations may include sending a power-up request to the portion. The operations may further include sending, at the specified amount of time after the power-up request, a write request for a write operation at the portion. The operations may further include sending a read request that requests a read operation for data written by the write operation. The operations may further include determining, based on data received in response to the read request, whether the portion correctly performed the read operation and the write operation.

Abstract: A semiconductor device including: a sense amplifier; a branched line selectively connectable to the amplifier; a recycling arrangement selectively connectable to the branched line; an array of bit lines connected to corresponding memory cells; a multiplexer configured to selectively connect the branched line to a selected one of the memory cells through a corresponding line amongst the array of bit lines; and a controller configured to control the recycling arrangement and the multiplexer to perform intra-sense-amplifier recycling of a gleaned amount of charge (gleaned charge) recovered from a first read operation to a second read operation.

Abstract: A semiconductor memory device including a memory cell having a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions and a plurality of second regions, each of the first regions and each of the second regions including one of the memory cells, each of the second regions further includes at least two first voltage providing contacts, and at least one second voltage providing contact, wherein the first voltage providing contacts and the second voltage providing contact are not located within each first region.

Abstract: A memory device includes a pass/fail check circuit configured to compare the number of memory cells, which are verified as being a program fail based on a result of verifying program operations of a first group of memory cells of a plurality of memory cells, with a first reference bit number, and to check whether the first group of memory cells is a pass or fail and a control circuit configured to control the pass/fail check circuit to recheck whether the first group of memory cells is the pass or fail based on a second reference bit number smaller than the first reference bit number when the first group of memory cells is found to be the pass based on a result of a pass/fail check operation of the pass/fail check circuit.

Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.

Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.

Abstract: A method for managing a plurality of data blocks of a data storage device includes steps of: reading a plurality of data pages in the data blocks which having valid data; updating a plurality of access counts of the data pages in the data blocks; determining whether an access count of the data block is greater than or equal to an access count threshold, wherein the access count of the data block is selected from one of the access counts of the data pages therein; and when the determination is positive, storing data in the data block into a spare data block of the data blocks. The access count threshold is updated when an erase count of the data block is determined to be greater than or equal to an erase count threshold. A method of data management for a data storage device is also provided.

Abstract: A data storage device includes a first data storage medium having a first capacity and a first speed, a second data storage medium having a second capacity and a second speed, and a device controller for interfacing between the data storage device and a host system. The second capacity is greater than the first capacity and the second speed is slower than the first speed. The device controller presents the data storage device to the host system as having a device capacity at least equal to the second capacity and a device speed at least equal to the first speed. The first data storage medium may be a solid-state drive while the second data storage medium is a hard disk drive. The device controller may be a solid-state drive controller, or a hard disk drive controller that may accept at least one solid-state drive command, such as a TRIM command.

Abstract: Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.

Abstract: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M<N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers.

Abstract: Various implementations described herein may refer to and may be directed to using port modes with memory. In one implementation, a memory device may include access control circuitry used to selectively activate one of a plurality of first word-lines based on first address signals from a first access port, and used to selectively activate one of a plurality of second word-lines based on assigned address signals. The access control circuitry may include address selection circuitry configured to select the assigned address signals based on a port mode signal, where the address selection circuitry selects the first address signals as the assigned address signals when the port mode signal indicates a single port mode, and where the address selection circuitry selects second address signals from a second access port as the assigned address signals when the port mode signal indicates a dual port mode.

Abstract: Phase change memory devices, systems, and associated methods are provided and described. Such devices, systems, and methods manage and reduce voltage threshold drift to increase read accuracy of phase change memory.

Abstract: A memory management method, and a memory control circuit unit and a memory storage apparatus using this method are provided. The method includes performing a first garbage collection operation corresponding to a data area if the number of physical erasing units associated with the data area is larger than a first threshold; performing a second garbage collection operation corresponding to a table area if the number of physical erasing units associated with the table area is larger than a second threshold; and dynamically adjusting the second threshold according to the number of the physical erasing units associated with the data area.