Abstract: Various aspects provide for a new combination of non-volatile memory architecture and memory processing technology. A memory cell has a gate node, a source node and a drain node. The gate node is connected to a wordline of the memory, the source node is connected to a local source line of the memory, and the drain node is connected to a local data line of the memory. A channel-based processing component programs the memory cell and inhibits programming of a second memory cell on the wordline of the memory. The channel-based processing component also grounds the local source line and the local data line in conjunction with programming the memory cell, and floats a second local source line and a second local data line connected to the second memory cell in conjunction with inhibiting programming of the second memory cell.

Abstract: Circuits for estimating threshold voltages of transistors in memory device bitcells are provided. The circuits use a multiplexer, a sensor switch network, a power switch network, and an NMOS device configured as a sensor to couple a desired one the transistors in the bitcells and the NMOS device to each other, to a test voltage, and to ground. A sensor voltage node can then be measured, and based on the resulting measurement, a threshold voltage for the transistor estimate.

Abstract: A semiconductor apparatus includes: a command control unit configured to decode external signals and generate a read strobe signal or a write strobe signal; a clock enable signal generation unit configured to activate one of a read clock enable signal and a write clock enable signal in response to the read strobe signal or the write strobe signal; and a clock control unit configured to generate a first control clock signal and a second clock control signal in response to an internal clock signal, the read clock enable signal, and the write to clock enable signal.

Abstract: In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row.

Abstract: Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs from the first set. Either the first set of periodic signals or the second set of periodic signals may be selected and used to generate a set of data capture signals. The selection of either the first set or the second set may be made on the basis of the number of serial data digits in a previously captured burst of data. The data capture signals may then be used to capture a burst of serial data digits.

Abstract: Memory, and erasing, programming and reading method thereof are provided. In the memory, a first isolation cell, a second isolation cell and a memory cell have same structure. A first doped region of the memory cell and a second doped region of the first isolation cell are connected with a first bit line, a second doped region of the memory cell and a first doped region of the second isolation cell are connected with a second bit line. A first doped region of the first isolation cell serves as a connection terminal thereof, first and second control gate structures of the first isolation cell are connected together to serve as a control terminal thereof, a second doped region of the second isolation cell serves as a connection terminal thereof, first and second control gate structures of the second isolation cell are connected together to serve as a control terminal thereof.

Abstract: A voltage division circuit, a circuit for controlling operation voltage and a storage device are provided. The voltage division circuit includes: a receiving transistor; a transistor group including m transistors connected in series; n type-one switches, each of which includes three terminals, the first is connected with a drain of a former one and a source of a latter one of two adjacent transistors in the transistor group, the second is connected with ground, the third is adapted for receiving a timing control signal; and n+1 type-two switches, each of which includes three terminals, the first is connected with a source of a transistor in the transistor group, the second is adapted for outputting a divided voltage, and the third is adapted for receiving the timing control signal. The voltage division circuit can save chip area, and work properly under a condition that the voltage to be divided is low.

Abstract: Method for writing to a MRAM cell including a magnetic tunnel junction including a first and second ferromagnetic layer, and a tunnel barrier layer; and a bipolar transistor in electrical connection with one end of the magnetic tunnel junction, the bipolar transistor being arranged for controlling the passing and polarity of a heating current in the magnetic tunnel junction. The method includes a sequence of writing steps, each writing step including passing the heating current in the magnetic tunnel junction such as to heat it to a high temperature threshold; and once the magnetic tunnel junction has reached the high temperature threshold, adjusting a second magnetization of the second ferromagnetic layer for writing a write data; wherein during one of the writing steps, the polarity of the heating current is reversed from one during the subsequent writing step. The method allows for an increased lifespan of the MRAM cell.

Abstract: A method includes defining a normal voltage configuration for application to word lines (WLs) and Bit lines (BLs) of a memory block, and a an abnormal voltage configuration, different from the normal voltage configuration, for application to the WLs and the BLs of the memory block when a word-line-to-word-line (WL-WL) short-circuit is found between at least two of the WLs in the memory block. If no WL-WL short-circuit is found in the memory block, a data storage operation is performed in the memory block by applying the normal voltage configuration. If a WL-WL short-circuit is found in the memory block, the data storage operation is performed in the memory block by applying the abnormal voltage configuration.

Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.

Abstract: A semiconductor device includes a first semiconductor chip located over a substrate; and a second semiconductor chip located over the first semiconductor chip, wherein the first semiconductor chip includes a first internal power supply generation circuit that generates a first internal power supply voltage supplied to a first internal circuit; a first penetration electrode formed from an upper surface of the first semiconductor chip to an underside of the first semiconductor chip and electrically connected to the first internal power supply generation circuit; a first reference voltage generation circuit that generates a first reference voltage; and a second penetration electrode formed from the upper surface of the first semiconductor chip to the underside of the first semiconductor chip and electrically connected to the first reference voltage generation circuit.

Abstract: To stably control a threshold voltage of a functional circuit using an oxide semiconductor. A variable bias circuit, a monitoring oxide semiconductor transistor including a back gate, a current source, a differential amplifier, a reference voltage source, and a functional circuit which includes an oxide semiconductor transistor including a back gate are provided. The current source supplies current between a source and a drain of the monitoring oxide semiconductor transistor to generate a gate-source voltage in accordance with the current. The differential amplifier compares the voltage with a voltage of the reference voltage source, amplifies a difference, and outputs a resulting voltage to the variable bias circuit. The variable bias circuit is controlled by an output of the differential amplifier and supplies voltage to the back gate of the monitoring oxide semiconductor transistor and the back gate of the oxide semiconductor transistor included in the functional circuit.

Abstract: Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor.

Abstract: The invention is provided to suppress a current supplied to a storage element so as not to vary for each layer in a semiconductor memory device obtained by connecting a plurality of memory cells in series. A semiconductor memory device according to the invention includes a plurality of memory cells connected in series between a first signal line and a second signal line, and supplies a different gate voltage to at least two of selection transistors included in the memory cells, respectively (refer to FIG. 2).

Abstract: A programmable logic device includes: a first memory element including a first electrode connected to a first wiring line, a second electrode, and a first resistive change layer, a resistance between the first and second electrodes being changed from a low-resistance state to a high-resistance state by applying, to the second electrode, a voltage higher than a voltage applied to the first electrode; a second memory element including a third electrode connected to the second electrode, a fourth electrode connected to a second wiring line, and a second resistive change layer, a resistance between the third and fourth electrodes being changed from a low-resistance state to a high-resistance state by applying, to the fourth electrode, a voltage higher than a voltage applied to the third electrode; and a first transistor, of which a gate is connected to the second electrode and the third electrode.

Abstract: An electronic device includes semiconductor memory, and the semiconductor memory includes a contact plug which is disposed over a substrate and extends in a vertical direction; a variable resistance element which is coupled to the contact plug and includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer; and a third magnetic layer which surrounds a sidewall of the contact plug and has a same magnetization direction as the second magnetic layer.

Abstract: An integrated circuit includes a reference voltage level setting circuit and a reference voltage generation circuit. The reference voltage level setting circuit is configured to set a level of an input reference voltage to a preset level in a power-up period or a self-refresh mode. The reference voltage generation circuit is configured to select one of a plurality of reference voltages and output the selected reference voltage as the input reference voltage when the power-up period is ended and an operation mode is not in the self-refresh mode.

Abstract: A repair information storage circuit may include a fuse block, a controller, and a fuse latch array. The fuse block provides a boot-up enable signal and repair information. The controller generates a voltage control signal in response to the boot-up enable signal. The fuse latch array stores repair information provided from the fuse block. The voltage control signal, which is used as a bulk bias of a transistor formed in the fuse latch array, is adjustable.

Abstract: A resistive memory device includes a cell block having a plurality of unit memory cells in which a resistive element and a cell select element are connected to each other in series, the cell block operating in response to a word line, a bit line, and a source line, and a dummy line, when different interconnection layers form the source line and the bit line, respectively, connected to one of the interconnection layers which is formed at a lower side the remaining interconnection layer between the interconnection layers for the source line and the bit line, wherein the dummy line has a resistance lower than a resistance of the lower interconnection layer.

Abstract: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M<N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers.